Senior RTL Engineer

Velaura AI develops ultra-low-power compute technology for cloud, edge, and physical AI applications. It also offers Teraflux Bitcoin mining hardware, fleet-management software, and related support for mining operators.

About Velaura AI

Velaura AI is a semiconductor and technology company that provides patented ultra-low-power silicon design technology, IP, toolflows, and custom chiplet solutions for AI compute platforms. Its customers include hyperscaler and XPU companies seeking reduced power consumption and higher compute efficiency. The company also builds Teraflux Bitcoin mining products, including air-, hydro-, and immersion-cooled miners, ASICs, modular containers, miner firmware, fleet-management software, and enterprise customer support.

Skills

• Cache
• Computer Architecture
• DMA
• ECC
• Hardware-Software Co-Design
• Interconnect
• IOMMU
• Memory Subsystem
• Microarchitecture
• NoC
• Performance Optimization
• Power Management
• RTL
• Silicon Bring-Up
• SMMU
• SystemVerilog
• Verilog

About The Role

You will own and optimize RTL for key portions of a Physical AI SoC. You will drive microarchitectural decisions, define hardware interfaces and memory hierarchies, contribute to data movement and control infrastructure, analyze bottlenecks, lead reviews, and mentor junior engineers.

Requirements

• 8+ years designing RTL for complex digital systems or equivalent depth
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
• Expert-level Verilog and SystemVerilog skills
• Experience with lint, CDC, synthesis-aware coding, and low-power intent
• Strong understanding of performance, power, and area tradeoffs
• Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures
• Experience with hardware/software co-design and system-level performance optimization
• Strong debugging and problem-solving skills

Responsibilities

• Own the design, implementation, and optimization of RTL for key SoC components
• Drive microarchitectural decisions
• Define hardware interfaces, execution flows, and memory hierarchies
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic
• Optimize designs for performance, power, area, scalability, and reliability
• Analyze performance bottlenecks and propose improvements
• Lead design reviews
• Mentor junior engineers

Pay

$200,000 – $500,000

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements

Schedule

Full time

Location: Santa Clara, CA (onsite)