Senior Engineer, Digital Verification

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

About the role

As a Senior Analog/Mixed-Signal (AMS) Design Verification Engineer at Analog Devices, you will own verification planning and execution for complex mixed-signal integrated circuits and subsystems. You will translate specifications into scalable verification architectures, develop reusable SystemVerilog/UVM and real-number modeling solutions, and drive coverage closure across digital, analog, and mixed-signal interfaces. Working independently with minimal supervision, you will partner with analog, digital, modeling, firmware, and validation teams to identify risk early, resolve complex failures, and deliver robust products from pre-silicon verification through silicon bring-up.

Responsibilities

• Verification Strategy and Planning: Own feature-based verification plans, requirements traceability, risk assessment, test strategy, and sign-off criteria for complex AMS IP, subsystems, and SoCs.
• AMS Verification Architecture: Architect scalable, reusable verification environments that combine SystemVerilog/UVM, analog behavioral models, real-number models, and mixed-signal simulation.
• Modeling and Abstraction: Develop and validate behavioral models in SystemVerilog real-number modeling, Verilog-AMS, or equivalent languages to accelerate full-chip verification while maintaining model fidelity.
• Test and Check Development: Create constrained-random and directed tests, scoreboards, reference models, assertions, monitors, and functional coverage for analog-digital interactions, control loops, power modes, calibration, and fault conditions.
• Coverage and Sign-Off: Define measurable code, functional, assertion, and requirements coverage goals; analyze gaps; drive closure; and communicate verification readiness and residual risk.
• Debug and Root-Cause Analysis: Lead cross-domain debug using waveforms, logs, assertions, schematics, and analog measurements to isolate failures involving timing, power sequencing, connectivity, modeling, and design behavior.
• Regression and Automation: Build reliable regression flows, triage infrastructure, dashboards, and automation that improve simulation throughput, reproducibility, and engineering productivity.
• Cross-Functional Execution: Collaborate closely with analog and digital designers, architects, firmware engineers, model developers, and post-silicon validation teams throughout the product lifecycle.
• Technical Leadership: Mentor engineers, lead reviews, establish verification best practices, and influence methodology, tool, and reuse decisions across projects.

Requirements

• SystemVerilog and UV