Senior Engineer Digital Verification and Methodology

About the role

WeAreIn for jobs that impact everyone's life. Turning customer whispers into industry shaking solutions... ready to amplify the future? As a Senior Engineer Digital Verification and Methodology on our Customer Collaboration and Technical Marketing team work hand-in-hand with our customers, enabling them to transform our products into cutting-edge designs, all while building long-lasting partnerships that thrive on success. Are you in? Your role Senior Engineer Digital Verification and Methodology: Join a collaborative verification methodology team that delivers high-quality integrated circuits through scalable environments, robust planning and continuous improvement. You will own key verification capabilities and partner across disciplines to elevate productivity, quality, and reuse.

Responsibilities

• Create verification plans and translate requirements into test scenarios, checkers, assertions and measurable coverage goals
• Develop and maintain SystemVerilog and UVM environments, reusable components and verification IP
• Execute constrained random and directed verification of digital modules and analyze regressions and coverage
• Develop, deploy and maintain reusable verification methodologies, automation and workflow standards across projects
• Own selected methodology capabilities including requirements definition, implementation, documentation, user enablement and continuous improvement
• Evaluate and apply AI-based methodologies for verification planning, test generation, debug, coverage analysis and workflow automation
• Collaborate with concept, design and application engineering teams and internal customers to communicate technical risks and drive verification and methodology scope to completion

Qualifications and Skills

• Mandatory: Degree in Electrical Engineering, Computer Engineering, Computer Science or related field and strong knowledge of digital circuit theory and hardware description languages such as SystemVerilog
• Mandatory: Hands-on experience in digital IC verification using SystemVerilog and UVM including constrained random, coverage-driven verification, regressions and debug
• Mandatory: Programming or scripting in C, Python or Perl and strong Linux skills
• Mandatory: Ability to work independently and collaborate across teams with strong communication, with English level Written and Spoken Fluent
• Preferred: Experience with formal verification, SystemVerilog assertions, firmware-driven verification or gate-level simulation
• Preferred: Knowledge of microcontroller-based ICs, safety or security requirements or complex protocols
• Nice to have: Experience improving and owning shared methodologies, enabling users, coordinating technical contributors or applying AI-based engineering approaches

Pay

Salary pay information: Location Indicative salary range Lexington, KY, United States Wage range that the company expects to pay for a qualified candidate: US$77,360 – US$116,040. In addition, all employees will be eligible to participate in an incentive plan.