Senior Development Test Engineer — Pre & Post-Silicon Software Test, Validation and Characterization

About the Role

We are seeking an experienced professional to own the end-to-end testing, characterization, and failure analysis strategy for complex, next-generation multi-die packages. You will own the complete validation lifecycle across a multi-die architecture, covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), PCIe/CXL subsystems. Additionally, you will apply statistical analysis and machine learning to test data, driving outlier detection, bench-to-ATE correlation, and predictive telemetry signals, without treating ML models as a substitute for true physical root-cause analysis.

Responsibilities

• Test Content and Automation:
  • Define development test strategies, coverage targets, content architecture, and strict traceability from architectural requirements to validation evidence.
  • Write low-level C and Python test suites, including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.
  • Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration for continuous validation.
  • Develop lab-to-ATE correlation test suites and drive smooth handoffs to Product & Test Engineering (PTE).
• Characterization and Margin Injection:
  • Build minimally invasive fault-injection hardware/software infrastructure that perturbs target datapaths without destabilizing the test setup itself.
  • Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
  • Validate system firmware error handlers, watchdog timers, and hardware-level fault containment behavior under out-of-spec conditions.

Qualifications

• Experience: 8–10+ years in post-silicon validation, system software testing, silicon bring-up, or development test for complex SoCs / ASICs / GPUs.
• Software/Firmware Skills: Advanced proficiency in C and Python for low-level bare-metal test content, hardware abstraction, and automation frameworks.
• Silicon Characterization: Proven experience with Shmoo plotting, PVT corner testing, jitter/margin analysis, and guard-band definition.
• Fault Injection Expertise: Hands-on experience building or executing error-injection and recovery validation campaigns on production silicon.
• Lab Instrumentation: Fluency with oscilloscopes, protocol analyzers (PCIe/CXL), logic analyzers, BERTs, thermal chambers, controllable power supplies, and JTAG debuggers.
• High-Speed & System Protocols: Practical, protocol-level understanding of high-speed serial interfaces (PCIe, CXL, or UCIe) and control buses (I2C, SPI, UART, PMBus, SMBus).
• Power Systems: Solid grasp of system power delivery, including sequencing, PMIC telemetry, DVFS, voltage regulation, and protection trip limits.
• Data & Tooling: Competency with toolchains (Git, CMake, GCC/Clang, CI pipelines) and statistics/data analysis over test populations.
• Education: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• AI Tool Usage: AI coding and automation tool is a must for this role.

Pay

The pay range for this role is $180,000 - $216,000 USD per year (US). This represents total target cash compensation, including both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location. This position is also eligible for equity in the form of stock options.

About TYLsemi, Inc.

TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems work at scale. We're solving the critical path problem of connecting hundreds of chips, delivering clean power, and moving terabits of data without compromising performance.

Culture & Team

• No Politics, No Bureaucracy: Flat structure, direct impact, and a focus on results.
• Remote-Friendly, Global Team: US team (Bay Area preferred) and a growing design center in Bangalore, India.
• Move Fast, Ship Real Products: Paying customers, committed capital, and aggressive timelines.

What We Value

• Ownership mindset
• Bias for action
• Deep technical expertise
• Low ego, high standards