Senior ASIC Verification Engineer

About the role

Join NVIDIA’s ASIC Verification team and help ensure the integrity and excellence of our industry-leading SoCs and GPUs. Your work will shape products across consumer graphics, autonomous vehicles, and artificial intelligence. As part of a global team, you’ll collaborate on the micro-architecture, design, verification, implementation, and post-silicon validation of groundbreaking automotive and gaming console chips, focusing on backbone IPs for ARM-based System on-chips.

Responsibilities

• Verify the design and implementation of leading SoCs to achieve first-pass silicon success.
• Lead the verification of ASIC design, architecture, golden models, and micro-architecture using UVM and other sophisticated methodologies.
• Define verification scope and develop robust infrastructure to verify complex logic.
• Collaborate with architects, designers, and pre-/post-silicon verification teams to drive comprehensive coverage.
• Innovate by integrating AI and LLM-driven workflows to optimize testbench generation, debug productivity, and coverage closure.

Requirements

• BS or equivalent in Electrical Engineering, Computer Engineering, or Computer Science; advanced degrees (MS, PhD) are a plus.
• 8+ years of experience in ASIC verification at both the IP and SoC level.
• Proven experience building UVM testbenches from scratch and applying constrained random methodology in production.
• High proficiency in C/C++ for developing architectural golden models and hardware-software co-verification tests.
• Deep domain knowledge in Low-Speed IOs (QSPI, UART, I2C), AXI/APB interconnects, DMA controllers, and Memory Controllers.
• Expertise in assertion-based design checks (SVA), code coverage, functional coverage, and formal test plan documentation.
• Strong debugging and analytical skills with a methodical approach to resolving complex SoC-level corner cases.
• Professional-grade scripting abilities in Python, Perl, or TCL to automate build flows and regressions.

Skills

• Advanced UVM architecture knowledge and large-scale SoC verification experience (a plus).
• Forward-thinking mindset with demonstrated ability to use AI tools to accelerate engineering tasks.
• Experience with Testbench Build flows, Makefiles, and version control (Perforce).
• Ambitious, highly motivated, and collaborative in a fast-paced environment.

Pay

Base salary ranges: $168,000–$264,500 USD (Level 4) or $196,000–$310,500 USD (Level 5), determined by location, experience, and comparable roles. Eligible for equity and benefits.