Senior ASIC Verification Engineer

About the role

The NVIDIA Clocks Team is seeking a Senior ASIC Verification Engineer with extensive experience in Design Verification. The team focuses on delivering high-quality clocking and reset logic for various units in System On Chips (SOC) and Graphics Processing Units (GPU) ASICs. The complexity of these designs has grown significantly, necessitating advanced verification techniques to ensure a bug-free design.

Responsibilities

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle sophisticated problems and develop scalable solutions applicable across different platforms.
• Work with industry-standard tools and state-of-the-art verification methodologies, including coding in System Verilog, UVM, C++, Perl, Python, and NVIDIA custom compilers and tools.
• Partner closely with the clocks architecture and design team to validate clocking designs.
• Coordinate with internal and external teams across time zones.

Requirements

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in industry-standard verification flows such as SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
• Exposure on block level and system-level verification.
• Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre-silicon platforms.
• Understanding of DFT/IST is optional.

Qualifications

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in industry-standard verification flows such as SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
• Exposure on block level and system-level verification.
• Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre-silicon platforms.
• Understanding of DFT/IST is optional.

Skills

• System Verilog
• UVM
• C++
• Perl
• Python
• Experience with NVIDIA custom compilers and tools

Benefits

• NVIDIA offers competitive compensation packages, including base salaries ranging from $136,000 to $218,500 for Level 3 and $168,000 to $264,500 for Level 4, based on location, experience, and the pay of employees in similar positions.
• Equity and benefits are also provided.

Pay

• Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

Schedule

• Not specified.

Benefits

• Not specified.

Company Information

• NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We highly value diversity in our current and future employees.