Senior ASIC Research Engineer – Front-end Digital Design

About the role

USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications, and artificial intelligence technologies. ISI’s 400 faculty, professional staff, and graduate students carry out extraordinary information sciences research at three locations: Arlington, VA; Marina Del Rey, CA; and Waltham, MA. The Computational Systems & Technology Division has an opening in Arlington, VA for a Senior ASIC Research Engineer – Front-end Digital Design to design advanced ASIC prototypes addressing problems of national importance. The Engineer will work with a cutting-edge team in a collaborative, flexible university setting with rich learning and growth opportunities, gaining experience in a fast-moving research environment alongside sponsors such as DARPA, IARPA, and the CHIPS Act.

Responsibilities

• Design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications such as communications, signal processing, and security
• Collaborate with ISI’s MOSIS 2.0 service
• Integrate third-party IP cores
• Work with top research sponsors (DARPA, IARPA, CHIPS Act)

Requirements

• Ability to handle Controlled Unclassified Information (CUI); per U.S. government regulations, eligibility requires U.S. Citizenship or Permanent Residency
• Degree in Computer Engineering, Electrical Engineering, or related field
• Master’s degree with more than 5 years of experience
• Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL
• Solid understanding of computer architecture and microarchitecture
• Demonstrated skills with EDA tools (logic synthesis, timing), scripting, and revision control
• Minimum education: Bachelor’s degree (combined experience/education may substitute)
• Minimum experience: 8 years
• Minimum skills: Experience with Linux; excellent written and oral communication skills

Qualifications

• Familiarity with digital design verification
• Familiarity with performance modeling
• Familiarity with agile hardware design methodologies
• Experience with AI-assisted workflows
• Experience using FPGAs
• Effective at verbal communication and giving clear explanations
• Preferred education: Master’s degree
• Preferred experience: 10 years
• Preferred skills: Proven leadership ability; experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization

Benefits

• Work on exciting and engaging projects that have real-life impact
• Small project team environment allows for involvement across entire project lifecycle
• Quality work-life balance
• Opportunities for free, top-tier university education for you and your children
• Great benefits — medical to matched retirement

Pay

The annual base salary range for this position is $140,000 to $170,000. When extending an offer, the University of Southern California considers factors such as the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, and external market and organizational considerations.

Job ID: REQ20182058 | Posted: 10/22/2026