Senior Digital ASIC Design Engineer

Brookhaven National Laboratory’s Instrumentation Division develops state-of-the-art instrumentation for experimental research programs at the Lab and maintains expertise and facilities in specialized high-technology areas. Development is driven by current and anticipated research directions, impacting global programs that rely on advanced radiation detectors, readout electronics, data acquisition systems, and scientific instrumentation.

About the role

We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for high-energy physics, nuclear physics, photon sciences, quantum information science, and related efforts at BNL and with external partners.

In this role, you will lead the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members across the ASIC group, Instrumentation Division, and broader scientific community.

Our ASICs operate in extreme environments, meeting stringent power, timing, noise, and radiation requirements while integrating reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. Applications extend beyond BNL to national and international user facilities, shaping instruments used for scientific discovery and engineering advancements globally.

Responsibilities

• Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs.
• Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders.
• Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces.
• Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration.
• Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments.
• Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration.
• Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout.
• Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems.
• Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies.

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, applied physics, or a closely related field of study.
• Minimum seven (7) years of progressively responsible related work experience in digital ASIC design.
• Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs.
• Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation.
• Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems.
• Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges.
• Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams.

Preferred Qualifications

• Master’s or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study.
• Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions.
• Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications.
• Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route.
• Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols.
• Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment.
• Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation.
• Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs.

Schedule

This is a fully onsite position located at Brookhaven National Laboratory in Upton, NY.

Pay

The full salary range for this position is $115,000 - $145,000 per year. Salary offers will be commensurate with the final candidate’s qualification, education, and experience and considered with the internal peer group.

Benefits

Brookhaven National Laboratory offers a comprehensive employee benefits program, including health, retirement, and work-life balance initiatives. Review more information at BNL | Benefits Program.