ASIC Research Engineer- Front-End Digital Design

Job ID: REQ20182054 | Posted: 10/22/2026 | Location: Arlington, VA (on-site)

About the role

USC’s Information Sciences Institute (ISI), a unit of the Viterbi School of Engineering, is a world leader in advanced information processing, computing, communications, and artificial intelligence research. ISI’s 400 faculty, professional staff, and graduate students operate across three locations: Arlington, VA; Marina Del Rey, CA; and Waltham, MA.

The CS&T Division seeks an ASIC Research Engineer – Front-end Digital Design to design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications in communications, signal processing, and security. The engineer will collaborate with ISI’s MOSIS 2.0 service, integrate third-party IP cores, and engage with top research sponsors such as DARPA, IARPA, and CHIPS Act programs. The position offers a collaborative, flexible university environment with rich learning opportunities and the chance to work on problems of national importance.

Requirements

• Ability to handle Controlled Unclassified Information (CUI) — requires U.S. Citizenship or Permanent Residency per U.S. government regulations
• Degree in Computer Engineering, Electrical Engineering, or related field
• Bachelor’s degree with more than 3 years of experience, or Master’s degree
• Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL
• Solid understanding of computer architecture and microarchitecture
• Demonstrated skills with EDA tools, scripting, and revision control
• Experience with Linux

Preferred Qualifications

• Experience using logic synthesis and timing tools
• Familiarity with digital design verification
• Familiarity with performance modeling
• Familiarity with agile hardware design methodologies
• Experience with AI-assisted workflows
• Experience using FPGAs
• Effective verbal communication and clear explanation skills
• Proven leadership ability
• Experience with artificial intelligence, very large-scale integration (VLSI) design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization

Pay

Annual base salary range: $115,000 – $140,000. Actual offer considers scope and responsibilities, candidate experience, education, key skills, internal equity, applicable laws, contractual stipulations, grant funding, and external market conditions.

Benefits

• Work on exciting, high-impact projects with real-life applications
• Small project teams enabling involvement across the entire project lifecycle
• Quality work-life balance
• Free, top-tier university education for you and your children
• Comprehensive benefits including medical coverage and matched retirement contributions

Skills

Required: Linux

Preferred: Leadership, AI/ML/deep learning (TensorFlow, PyTorch, HuggingFace), VLSI design, Dockerization