Senior ASIC Hardware Design Engineer

About the role

NVIDIA is seeking ASIC Design Engineers to join the NVLink ASIC Design team. This role involves designing and implementing the next generation of NVLink protocol and GPU subsystem logic, contributing to micro-architecture development, and ensuring designs are functionally, performantly, and physically implementable.

Responsibilities

• Engage in and support the design and development of NVIDIA’s next-generation NVLink protocol and GPU subsystem logic.
• Contribute to micro-architecture development and document specifications of GPU and interconnect sub-systems.
• Implement in RTL and debug while collaborating with the verification team to ensure that the design is functional and performant.
• Apply logic design skills to optimize and meet performance and power goals.
• Deliver a synthesis/timing clean design while collaborating with the physical design team to ensure a routable and physically implementable solution.
• Support hardware engineering activities including chip floor plan, power/clock distribution, chip assembly, timing closure, power and noise analysis, and back-end verification.
• Develop flows and tools as necessary in support of design activities.

Requirements

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience and 5+ years of industry experience.
• Strong practical understanding of Verilog and/or SystemVerilog.
• Relevant project experience in micro-architecture and RTL development of complex designs.
• Exposure to computer architecture and digital systems designs.
• Highly proficient in logic development, Verilog and/or SystemVerilog, with an understanding of physical implementation and VLSI.
• Strength in scripting languages such as Perl or Python.
• Strong collaboration and communication skills.

Qualifications

• Background with low-power build methodologies.
• Experience with high-speed build methodologies.
• Proven track record of successfully implementing complex designs.

Skills

• Logic design skills.
• Verilog and/or SystemVerilog proficiency.
• Scripting languages (Perl or Python).
• Collaboration and communication skills.

Benefits

• Competitive salaries.
• Generous benefits package.
• Equity eligibility.

Pay

Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

Schedule

Not specified.

Application Instructions

Applications for this job will be accepted at least until July 6, 2026. This posting is for an existing vacancy.