Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs
About the team
Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a foundational role in the project by automating design flows and building large-scale solutions that accelerate silicon development and we're just getting started here at Amazon!
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help.
About the role
We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality.
Core responsibilities
- Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.
- Enhance and build design flows to boost the overall productivity of design teams.
- Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.
Basic qualifications
- 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
- 7+ years of digital design in communication systems experience
- 7+ years of full-custom analog or RF layout experience
- 7+ years of wireless communications systems and implementation experience
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
- 7+ years of verification in communication systems experience
- 5+ years of UVM, C, System C, and scripting experience
Preferred qualifications
- Master's degree or Ph.D. degree in Electrical Engineering or related field
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation
What we offer
- Work/life balance: we strive for flexibility as part of our working culture
- Inclusive team culture with employee-led affinity groups and ongoing learning experiences
- Mentorship and career growth resources including endless knowledge-sharing and career-advancing resources
- Sign-on payments and restricted stock units (RSUs)
- Comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave
Pay
- USA, CA, Cupertino: $183,000.00 - $247,600.00 USD annually
- USA, TX, Austin: $159,200.00 - $215,300.00 USD annually