Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

About the team

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help

Key job responsibilities

• Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.
• Enhance and build design flows to boost the overall productivity of design teams.
• Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.

Basic Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
• 7+ years of digital design in communication systems experience
• 7+ years of full-custom analog or RF layout experience
• 7+ years of wireless communications systems and implementation experience
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
• 7+ years of verification in communication systems experience
• 5+ years of UVM, C, System C, and scripting experience

Preferred Qualifications

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation