RTL2GDS, Senior Principal Design Engineer

About the role

The Senior Principal Solutions Engineer at Cadence supports the adoption of Cadence products to help chip designer customers achieve superior performance for their Design PPA goals. This role focuses on Place and Route (with a primary emphasis on Place and Route), Synthesis, STA/SDC, and Multivoltage design implementation.

Responsibilities

• Support the adoption of Cadence products to help chip designer customers achieve superior performance for their Design PPA goals.
• Support strategic customer evaluations/benchmarks on Cadence’s front-end solutions to establish technology differentiation and assert Cadence competitive advantages.
• Manage and own block implementation, top-level implementation, and sign-off focused efforts in RTL to GDSII delivery of projects.
• Drive best practices and lessons learned from evaluations/benchmarks and customer interactions back into product development and Cadence field engineers.
• Assist customers with adopting Cadence Front End tools in Synthesis with Genus DFT & Scan with Encounter Test (ET) by providing methodology and tool knowledge to IC design processes, validated through successful design tapeouts.
• Develop an understanding of the customer's needs and also of the competition's technology and sales strategies.
• Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services.
• Aid sales staff in assessing potential applications of company products to meet customer needs and prepare detailed product specifications.
• Create and conduct technical presentations and product demonstrations to customers.

Requirements

• 7+ years of experience and strong technical knowledge of Cadence products.
• Senior Level Applications Engineer position with deep knowledge of Cadence or Synopsys place and route tools.
• Experience with low power and multi-voltage design techniques, especially relevant for leading-edge wireless and mobile customers.
• Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digital Implementation Platform.
• Ability to manage and prioritize multiple issues and exploit new technologies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• BS degree+ - NOT AN ENTRY LEVEL POSITION.

Skills

• Strong technical knowledge of Cadence products.
• Experience with Synthesis, Place and Route, STA/SDC, and Multivoltage design implementation.
• Experience with low power and multi-voltage design techniques.
• Experience with Encounter Digital Implementation Platform.
• Ability to manage and prioritize multiple issues and exploit new technologies.

Benefits

• Opportunity to gain experience in methodology, product delivery, and working on cutting-edge technology.

Pay

• Competitive compensation package.

Schedule

• Full-time position.