RTL2GDS Principal Product Engineer

About The Opportunity

Cadence's Digital and Signoff Group (DSG) is seeking a seasoned Principal Product Engineer to lead technical excellence across their digital implementation product portfolio. This role involves serving as a senior technical authority, bridging Cadence's R&D organization with strategic customers, and shaping the roadmap of key products like Innovus, Tempus, and Genus.

What You Will Do

• Own complex, high-priority customer escalations from diagnosis through resolution, acting as the senior technical point-of-contact for strategic accounts.
• Lead the development and execution of advanced design benchmarks targeting 7nm, 5nm, 3nm, and next-generation nodes, focusing on PPA optimization and runtime performance.
• Partner with Cadence R&D architects to identify product gaps, propose algorithmic improvements, and validate new feature releases.
• Define and develop reference methodologies and best-practice flows for hierarchical and flat design implementation using the full Cadence digital toolchain.
• Mentor junior and senior product engineers, providing technical guidance and code/flow reviews on complex implementation challenges.
• Drive automation initiatives in Tcl, Perl, Python, and Shell to build scalable infrastructure for regression testing, benchmarking, and customer flow replication.
• Represent Cadence DSG in customer technical reviews, design-for-manufacturability (DFM) workshops, and industry conferences.
• Influence product roadmap decisions by synthesizing customer feedback, competitive landscape insights, and internal R&D capabilities into actionable recommendations.

What You Bring

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 6–8 years of deep, hands-on experience in ASIC physical design and/or EDA product engineering, with a demonstrable track record of shipping designs or product improvements.
• Expert-level understanding of the full RTL-to-GDSII flow: synthesis, floor-planning, placement, CTS, routing, static timing analysis, and physical sign-off.
• Proven experience with timing closure and PPA optimization at 16nm and below — including 10nm, 7nm, and 5nm FinFET processes.
• Deep proficiency with Cadence Innovus Implementation System, Tempus Timing Signoff Solution, and Genus Synthesis Solution; familiarity with Pegasus Physical Verification is a strong asset.
• Advanced expertise in static timing analysis: multi-mode multi-corner (MMMC), POCV/AOCV, hold-time optimization, and clock domain crossing (CDC) methodology.
• Thorough understanding of hierarchical design methodologies — interface timing modeling (ITM/ETM), blackbox flows, and top-level integration.
• Extensive knowledge of low-power design: IEEE 1801 UPF, multi-voltage domains, power gating, retention strategies, and dynamic voltage/frequency scaling.
• Strong scripting and automation skills: Tcl (advanced), Perl, Python, and Shell; experience building reusable flow infrastructure is highly valued.
• Demonstrated leadership in technical problem-solving with an organized, data-driven approach and the ability to influence cross-functional teams.
• Excellent communication skills — able to present complex technical content clearly to executive stakeholders, customers, and R&D partners alike.
• Leadership & Soft Skills:
  • Proven ability to lead cross-functional technical projects, from initial scoping through delivery and documentation.
  • Experience in customer-facing roles with the gravitas to manage high-stakes technical discussions under pressure.
  • Comfort operating independently in a fast-paced, matrix organization while driving accountability and results.
  • Passion for staying at the forefront of semiconductor design trends, with an ability to translate emerging challenges into product opportunities.

Nice to Have

• Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows.
• Knowledge of advanced routing constraints: self-aligned double patterning (SADP), EUV-specific design rules, and advanced via optimization.
• Familiarity with chip design in automotive (ISO 26262), AI/ML accelerator, or HPC application domains.
• Prior experience in an R&D engineering role at an EDA or semiconductor company.

Why Cadence?

Shape the future of EDA — your work directly influences tools used to design next-generation processors, SoCs, and AI chips. Collaborate with a high-caliber team of engineers working on the world's most complex implementation challenges. Enjoy a competitive total compensation package including equity, performance bonuses, and comprehensive benefits. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.