RFIC Silicon Lead

About the role

We are building CMOS RF systems at ultra low-power envelopes. We are looking for our first silicon hire: the person who will define the RF CMOS architecture, translate Tacit’s sensing and ML constraints into circuit reality, and set the technical foundation for everything that follows. This role starts hands-on. You will work at the transistor level, stand up the initial design environment, evaluate process options, simulate and design critical blocks, and drive early silicon decisions.

Responsibilities

• Define the RF CMOS architecture for an ultra-low-power, frequency-agile sensing front end
• Translate system-level sensing, ML, and form-factor constraints into circuit-level requirements
• Design and/or technically direct critical RF circuit blocks, including VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, biasing, and power-management structures
• Architect fast-settling frequency generation and hopping approaches suitable for aggressive duty-cycled operation
• Drive power-reduction methodology across the RF system: duty-cycle co-design, supply gating, bias trimming, wake/sleep transients, and system-level power tradeoffs
• Evaluate and recommend CMOS process options for a low-power wideband / frequency-agile SoC, including tradeoffs across 28nm, 22FDX, 55nm RF, and related nodes
• Stand up and operate the early RFIC design environment, including Cadence Virtuoso, Spectre, ADE, EM simulation, Calibre, and PDK flows
• Identify when an architecture will not close in silicon, and propose practical relaxations or alternatives
• Own or technically direct implementation through DRC/LVS, tape-out, packaging, bring-up, measurement correlation, and iteration
• Evaluate, select, and technically manage external silicon partners where appropriate, while keeping architecture-defining IP and technical judgment inside Tacit
• Help build the future silicon team as the architecture, program, and company scale

Requirements

• MS or PhD in electrical engineering, or equivalent experience
• 10+ years in RFIC design, with substantial industry experience delivering silicon
• Deep experience in low-power CMOS RF, synthesizers, radar, UWB, frequency-agile radios, or related sensing systems
• Strong transistor-level design ability in Cadence Virtuoso, Spectre, and ADE
• Expertise in synthesizer and RF front-end circuits, especially VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, and biasing
• Strong understanding of CMOS process tradeoffs, device behavior, stack selection, parasitics, layout effects, and RF process-node selection
• Experience with EM simulation tools such as EMX, HFSS, Momentum, or equivalent
• Track record taking RFIC blocks or systems from architecture through silicon validation
• Ability to reason across architecture, circuits, layout, packaging, measurement, power, and product constraints
• Ability to translate ambiguous system-level goals into concrete circuit and silicon tradeoffs
• Strong communication skills and ability to lead technical decisions in a small, fast-moving team

Qualifications

• Background in low-power radar, UWB, frequency synthesizers, or frequency-agile sensing front ends
• Experience with fast-settling PLLs, wideband frequency generation, duty-cycled RF systems, or ultra-low-power sensing radios
• Experience with 28nm, 22FDX, 55nm RF, or other RF-capable CMOS processes
• Experience as a first or early silicon hire at a startup
• Experience managing external design houses, foundries, packaging vendors, or semiconductor supply-chain partners
• Experience with RF/analog/digital co-design and system-level power optimization
• Experience building, hiring, or mentoring RFIC teams
• Strategic mindset: engineering decisions framed in terms of business outcomes, product milestones, defensible IP, and time-to-market

Skills

• Strategic mindset

Benefits

• Competitive equity package
• Comprehensive medical, dental, and vision insurance
• Company size: 30-50 people
• Unlimited PTO
• Visa sponsorship
• 4% 401k matching

Compensation Range

$180,000 - $230,000/year plus meaningful equity package