Real-Time Budget Planner

We are looking for a 𝗥𝗲𝗮𝗹-𝗧𝗶𝗺𝗲 𝗕𝘂𝗱𝗴𝗲𝘁 𝗣𝗹𝗮𝗻𝗻𝗲𝗿. You'll build timing and memory tasks around a real-time system you have worked on, so a leading AI company can measure how well models handle real embedded engineering problems. 𝗘𝗻𝗴𝗮𝗴𝗲𝗺𝗲𝗻𝘁 𝗱𝗲𝘁𝗮𝗶𝗹𝘀:Location: MichiganWorking model: HybridStart date: ASAPEmployment type: Freelance – hourly rate: $70–90 (paid per accepted task) 𝗥𝗲𝘀𝗽𝗼𝗻𝘀𝗶𝗯𝗶𝗹𝗶𝘁𝗶𝗲𝘀:Build a benchmark environment around a real-time system you have worked on – an ECU, controller, flight or motor control unitInclude the task set and source code, MCU or SoC reference manuals and datasheets, RTOS configuration, linker map, measured timing traces, and the deadlines the system had to meetSet up the tools the work needs – cross-compiler, QEMU or an instruction set simulator, trace tools, Python, PDF tools, and a schedulability analysis tool if you use oneWrite five or more tasks, each built on a timing or memory decision or failure on that system (e.g. WCET bounds for park assist routines, core and priority layout for an ADAS controller under memory interference, rare controller resets after a software release)Frame each task so the model must produce answer.json with a WCET bound per routine, a core and priority assignment, or a memory layoutHide the deciding load where an engineer would have to dig for it – ISR and DMA bursts in the traces, bus or cache interference between cores, a clock setting in the reference manualWrite a hidden marking script that checks bounds against measured traces within a set tolerance and runs response-time analysis against every deadline and memory limit, scoring 0.0 to 1.0Supply your own answer (scoring 1.0) and a naive answer a competent engineer might give first (scoring below 0.3)Pitch task difficulty so frontier models solve it in 1 to 4 out of 10 runs, or fail all 10 for the evaluation set 𝗤𝘂𝗮𝗹𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻𝘀:Hands-on experience on a real-time embedded system – ECU, controller, flight or motor control unitStrong grasp of WCET analysis, response-time analysis and schedulabilityExperience with RTOS configuration, task priorities and multicore core assignmentAble to work from MCU or SoC reference manuals, datasheets and linker mapsExperience analysing timing traces, including ISR and DMA load and bus or cache interference between coresComfortable with cross-compilers, QEMU or instruction set simulators, and trace toolsPython skills to write automated marking scripts 𝗡𝗲𝘅𝘁 𝘀𝘁𝗲𝗽𝘀:Press "Apply"We will review your applicationIf qualified, you will be accepted into the network and can be considered for this and similar positions & projects We can only accept candidates that are willing to work as individual contractors / freelancers.