Product Engineer - Tessent DFT

Position Overview

The Tessent division seeks a highly motivated, creative, and energetic individual as Product Engineer, specializing in design-for-test (DFT) and test delivery at chip and system level. Tessent is the market and technology leader of automated tools for insertion of semiconductor design-for-test (DFT) structures, automatic test pattern generation (ATPG), embedded deterministic compression (EDT), memory built-in self-test (MBIST), logic built-in self-test (LBIST), diagnosis-driven yield analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test. This position presents a great opportunity to stay involved technically while getting exposure to marketing and interacting with sales.

Responsibilities

• Define and characterize new product capabilities needed to meet customer requirements
• Work collaboratively with Tessent R&D to prototype, evaluate, and test new products and features within complex IC design flows
• Lead beta programs and support beta partners
• Drive product adoption and growth
• Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes
• Develop and review tool documentation such as user and reference manuals
• Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing
• Work through complex technical issues and independently create solutions and new methodologies
• Present complex principles in simple terms to broad audiences
• Collaborate and share information across team boundaries in written and spoken forms
• Some travel, domestic and international

Qualifications

• BS degree (or equivalent) in Electrical Engineering, Computer Science, Computer Engineering, or related field
• 3-5 years of experience, including experience in DFT for complex ASICs / SOCs within one or more of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, hierarchical DFT implementation
• High energy, curious individual, self-motivated to learn new DFT methodologies and technologies
• Able to work as individual contributor within a global and diverse team
• Strong problem-solving, reasoning and deduction skills and the ability to analyze and debug complex design and simulation issues
• Proficiency in LINUX and Windows environments
• Proficiency in a scripting language like TCL (preferred) or Python
• Excellent written and spoken English language communication skills
• Excellent organizational skills

Preferred Knowledge, Skills & Experience

• Industry experience with DFT tools, preferably Siemens Tessent tool suite
• Experience with inserting scan, running ATPG and debugging fault coverage
• Exposure to one or more adjacent IC disciplines such as: RTL coding and verification using Verilog/SystemVerilog/VHDL; synthesis and timing analysis; place and route; advanced IC packaging; DFT and test for embedded IP cores; failure diagnosis; ATE use / test program development
• Prior experience as individual contributor as well as directing technical activities of junior engineers (mentoring or training)

Pay

$90,000 – $162,000