Principal Signal and Power Integrity Engineer

Responsibilities

• Deliver SIPI solutions that meet the HPC demands across the entire system.
• Drive future power delivery solutions for chiplet architecture with advanced packaging and advanced silicon nodes.
• Design, model, and simulate PI (i.e., incl. IP design, voltage regulator, motherboard, CPU package, silicon, and decoupling capacitor solution) for data center processors and corresponding platforms to ensure optimized performance.
• Perform DC, AC and transient simulation to provide noise, impedance profile of the whole power delivery path and link/electrical simulations to validate I/O performance from platform to silicon.
• Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.
• Drive engineering system design decisions that require collaboration between internal and external stakeholders to account for platform-specific technology decisions and develop system models based on current and anticipated feature/design needs and trade-offs.

Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
• Equivalent experience.

Preferred Qualifications

• MSEE degree with 10 years’ experience in silicon packaging products development
• Experience with power integrity modelling for HPC products
• Strong foundation in advanced packaging technologies as it relates Power integrity
• Experience with Foundry Silicon technologies, OSAT technologies and Substrate technologies
• MS degree with minimum 7+ years of experience in silicon/package/system power integrity/delivery
• BSEE degree with minimum 10 years’ experience in silicon/package/system power integrity/delivery
• Experienced in the field of Power Integrity and delivery, System design, IP design with knowledge on product development with minimum 7 years’ experience in design and electrical modelling
• Good working knowledge in the field of end to end system SIPI Design and Architecture
• Industry knowledge, trends and landscape of technologies to drive development across Silicon-IP, Advanced packaging, Substrate technology, Board technology and Platform design
• Interpersonal skills including written and verbal communication, teamwork, negotiation, and presentation