Principal Signal and Power Integrity Engineer

About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. The company’s Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

We seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute SI planning, design, modeling, simulation, and lab validation with various system configurations. This position is onsite.

Responsibilities

• Define hardware system constraints and high-speed technology roadmaps.
• Collaborate cross-functionally with the electrical design community to develop systems.
• Perform SI and PI design, simulation, and measurement for complex SoC/silicon products in Server and Networking applications.
• Conduct 2D and 3D EM simulations using Cadence/Ansys/ADS toolsets.
• Model BGA and connector structures electromagnetically.
• Simulate high-speed SERDES channels and equalization.
• Execute PI simulations with Ansys/Cadence toolsets.
• Use lab equipment such as VNA, TDR, real-time, and sub-sampling oscilloscopes for validation.
• Apply knowledge of PCB fabrication limits and trade-offs.
• Debug, analyze, and solve problems, leading root cause and corrective action teams.

Requirements

• Strong academic/technical background in electrical engineering; Bachelor’s degree required; Master’s preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
• Proven track record with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects.
• Familiarity with industry standards such as PCI-SIG and IEEE 802.3, especially Electrical sections.
• Self-starting, professional, and hands-on work ethic with the ability to execute intense research in a dynamic environment.
• Proven ability to solve problems independently, preferably as a tech lead.
• Entrepreneurial, open-minded behavior, and can-do attitude.
• Authorized to work in the US and available to start immediately.

Pay

The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level will be determined by years of experience and interview outcome.