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Jobs · Information Technology · Colorado

Principal Physical Design Engineering Lead ($400-500k)

CyberCoders · Fort Collins, CO · 2 mo ago
On-siteInformation TechnologyFull-time

Are you a seasoned Engineer who excels at guiding complex semiconductor programs across areas such as physical design, STA, DFT, and packaging and a passion for working on bleeding-edge AI and high-performance silicon? Have you delivered enough chips to recognize hidden issues in EDA reports before they impact schedules, and can you clearly explain both the technical root cause and the long-term solution? Do you enjoy deep technical discussions with engineering teams while also providing clear, high-level summaries to management?

About the role

As a senior technical leader (prior leadership experience NOT required), you will guide customer ASIC programs and ensure successful delivery of highly complex designs (approximately 80% hands-on, 20% technical leadership).

Responsibilities

  • Lead end-to-end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring-up, and production.
  • Advise customer teams on EDA best practices, design flows, and methodologies, including hosting Q&A sessions with technical experts.
  • Identify risks related to quality, schedule, or dependencies and coordinate mitigation plans with internal and external teams.
  • Run physical design validation flows to ensure incoming customer netlists meet strict tape-out quality requirements.
  • Stay up to date on new technologies, IP developments, and application trends.
  • Work closely with marketing, sales, legal, and compliance teams on program-related discussions.
  • Collaborate with and support other engineering teams as needed.

Requirements

  • Multiple tape-outs at advanced process nodes.
  • Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies.
  • Strong understanding of low-power design techniques and power management.
  • Hands-on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging.
  • Programming or scripting experience.
  • Excellent communication skills.

Nice-to-have

  • Exposure to SERDES communication protocols.
  • Experience in logic design, chip architecture, microarchitecture, Verilog RTL development, front-end verification, DRC, and logic synthesis.
  • Knowledge of DFT methods including scan, memory BIST, and repair.

Benefits

  • Health, dental, and vision insurance.
  • Life and disability insurance.
  • FSA and HSA.
  • 401k with match.
  • ESPP (Employee Stock Purchase Plan).
  • Generous PTO.
  • Annual bonus from 15-30% (depending on your level).
  • Very generous stock grants vesting over 4 years.

Pay

Up to $230k base salary, plus 30% bonus and approximately $800k–$1.2M in stocks vesting over 4 years. Realistic first-year total income: $450–500k.

Schedule

This is a full-time role.

Locations: San Jose, CA; Irvine, CA; or Fort Collins, CO. You must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa.

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