Physical Design Lead (Principal or Master Level - up to 800k)

ASIC Engineering Lead (Physical Design OR STA)Principal Level up to $550k, Master Level up to $880k total comp (base + bonus + stocks)Locations: San Jose, CA, Irvine, CA or Fort Collins, COIntroductionAre you a seasoned Engineer who excels at guiding complex semiconductor programs across areas such as physical design, STA, DFT, and packaging and a passion for working on bleeding-edge AI and high-performance silicon? Have you delivered enough chips to recognize hidden issues in EDA reports before they impact schedules, and can you clearly explain both the technical root cause and the long term solution? Do you enjoy deep technical discussions with engineering teams while also providing clear, high level summaries to management?If this sounds like you, and you want to work on advanced compute and infrastructure silicon, this role may be an excellent match.Top Reasons to Work With UsSupport customers building cutting edge ASICs in AI, HPC, networking, and storageCollaborate with highly experienced cross functional engineering and technology teamsInfluence the development of next generation semiconductor technologiesTake ownership of customer success from initial engagement through productionShape design methodologies, best practices, and implementation strategiesBe part of a supportive, collaborative environment that values technical leadershipThe Role / ResponsibilitiesAs a senior technical leader, (NOTE: prior leadership experience NOT required) you will guide customer ASIC programs and ensure successful delivery of highly complex designs. (Approximately 80% hands on, 20% technical leadership). Your responsibilities will include:Leading end to end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring up, and productionAdvising customer teams on EDA best practices, design flows, and methodologies, including hosting Q&A sessions with technical expertsIdentifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teamsRunning physical design validation flows to ensure incoming customer netlists meet strict tape out quality requirementsStaying up to date on new technologies, IP developments, and application trendsWorking closely with marketing, sales, legal, and compliance teams on program related discussionsCollaborating with and supporting other engineering teams as needed Essential SkillsMultiple tape outs at advanced process nodesAbility to analyze PPA tradeoffs across library components, architectures, and implementation strategiesStrong understanding of low power design techniques and power managementHands on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packagingProgramming or scripting experienceExcellent communication skillsBonus Points ForExposure to SERDES communication protocolsExperience in logic design, chip architecture, microarchitecture, Verilog RTL development, front end verification, DRC, and logic synthesisKnowledge of DFT methods including scan, memory BIST, and repairBenefitsHealth, dental, and vision insuranceLife and disability insurance FSA and HSA401k with matchESPPGenerous PTOAnnual bonus from 15-30% (depending on your level)VERY generous stocks! Email Your Resume In Word To Sally.Janavicius@CyberCoders.com Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply. Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : SJ2-1990411L958 -- in the email subject line for your application to be considered. Sally Janavicius - Principal Recruiter This is a new role. Employer is willing to sponsor qualified candidates for a non-immigrant work visa. This job was first posted by CyberCoders on 06/23/2026 and applications will be accepted on an ongoing basis until the position is filled or closed. This job was posted on 06/23/2026 and is open for 90 days Everforth CyberCoders is proud to be an Equal Opportunity Employer All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at Benefits@CyberCoders.com to make arrangements. Copyright © 2026 Everforth, Inc. All rights reserved.