Physical Design Technical Lead

About the role

We are seeking a highly accomplished Physical Design Technical Lead who thrives at the intersection of disciplined engineering excellence and bold technical innovation. In this role you will own complex SOC and block-level implementation challenges end-to-end — from floorplan and power intent through final signoff — while actively shaping the evolution of our ML/AI-driven implementation flows.

Responsibilities

• Own floorplan architecture and power domain partitioning for large, multi-million instance SOC designs
• Drive block-level implementation through synthesis, place-and-route, CTS, and ECO closure with sign-off quality results
• Lead cross-functional convergence on timing, power, and area targets across multiple concurrent tapeout projects
• Collaborate with RTL, DFT, packaging, and analog teams to resolve integration challenges proactively
• Define and enforce physical design guidelines, constraint authoring (SDC/UPF), and methodology standards
• Advanced Closure & Signoff
• Achieve full signoff closure: STA (multi-corner multi-mode), IR drop, electromigration, DRC/LVS, antenna
• Drive PPA optimization strategies including innovative floorplanning, clock topology, and routing resource planning
• Lead critical-path analysis and timing-driven ECO resolution in partnership with design and library teams
• Manage hierarchy and partitioning trade-offs for hierarchical vs. flat implementation flows
• ML/AI Flow Innovation
• Champion the integration of ML/AI-based optimization engines into production
• Hands-on experience with AI-assisted place-and-route, ML-based timing prediction, or reinforcement-learning PPA optimization
• Evaluate and productize emerging AI tools from EDA vendors and internal research teams
• Develop and maintain feedback loops between signoff results and ML training data pipelines
• Partner with CAD and automation teams to deploy AI-driven ECO, congestion prediction, and closure acceleration scripts
• Mentorship & Technical Leadership
• Mentor and technically guide a team of 3–8 physical design engineers across multiple project tracks
• Lead design reviews, closure reviews, and retrospectives; drive continuous improvement culture
• Represent Physical Design in architecture planning meetings and influence design-for-implementability decisions
• Contribute to internal white papers, methodology documentation, and IP reuse initiatives

Qualifications

• Minimum Qualifications:
• Master’s Degree In Electrical Engineering, Computer Engineering, Or a Related Discipline
• With 15+ Years Of Industry Experience In Physical Design, Physical Implementation, Or SoC Backend Design, Including The Following 15+ years of progressive experience in physical design, physical implementation, or SoC backend development for advanced semiconductor products.
• 4+ Years Of Experience In A Technical Lead, Senior Lead, Or Principal-Level Physical Design Role With Ownership Over Complex Physical Design Execution And Delivery
• 3+ Successful Tapeouts With Direct Hands-On Physical Design Ownership At Advanced Process Nodes, Including 7nm Or Below.
• 5+ Years Of SoC-Level Floorplanning, Top-Level Integration, And Full-Chip Physical Implementation Experience, Beyond Block-Level Physical Design Ownership.
• 10+ Years Of Hands-On Experience With Industry-Standard Physical Design Implementation Tools Such As Synopsys Fusion Compiler And/or Cadence Innovus.
• 8+ Years Of Experience Performing Static Timing Analysis And Timing Closure Using Tools Such As Synopsys PrimeTime, Including MMMC Analysis, SI/crosstalk Closure, And Path-Based Analysis.
• 5+ Years Of Hands-On Experience With Power Integrity Analysis And Signoff Using Tools Such As Ansys RedHawk Or Cadence Voltus For Static And Dynamic IR Drop And Electromigration (EM) Analysis.
• 5+ Years Of Experience Implementing Multi-Voltage And Low-Power Design Methodologies Using UPF And/or CPF, Including MTCMOS, Retention, Isolation, And Power Intent Implementation.
• 5+ Years Of Experience With Physical Verification And Signoff Flows Using Tools Such As Mentor Calibre DRC/LVS, With Exposure To Cadence PVS And/or Equivalent Signoff Tools.
• 8+ Years Of Scripting And Automation Experience In Physical Design Environments Using Tcl, With 3+ Years Of Experience Using Python, Perl, Or Similar Languages To Improve Design Flow Automation And Engineering Productivity.
• 2+ Years Of Experience Using Or Evaluating ML/AI-Driven Physical Design Tools Or Methodologies, Such As Synopsys DSO.ai, Fusion Compiler AI, Cadence Cerebrus, Or Equivalent Technologies.
• 2+ Years Of Experience Applying Or Supporting Custom ML/AI-Based Physical Design Workflows For Use Cases Such As Timing Prediction, Hotspot Detection, Congestion Modeling, Or PPA Optimization.
• 2+ Years Of Experience Interpreting ML Model Outputs, Design Metrics, Or Optimization Recommendations And Translating Them Into Actionable Physical Implementation Decisions.
• 2+ Years Of Experience Working With Python-Based Data Pipelines, Design Metric Collection, Result Analysis, Or Visualization Workflows In Support Of Physical Design Optimization.
• Preferred Qualifications:
• Experience With FPGA Or Structured-ASIC Fabric Implementation — Altera-Specific Knowledge Is A Distinct Advantage
• Exposure To 3DIC / Chiplet Integration: UCIe, EMIB, Hybrid Bonding Physical Design Constraints
• Prior Work On High-Speed I/O Integration (PCIe Gen 5/6, HBM PHY, SerDes) Within SOC Physical Implementation
• Contributions To EDA Vendor Beta Programs, Academic Publications, Or Conference Presentations (DAC, ICCAD, SLIP)
• Familiarity With Advanced Signoff (Path-Delay Rules, SI-Aware Fixing, Advanced Node Design Rule Awareness)
• Prior Experience At Semiconductor IP Companies, EDA Vendors, Or Top-Tier Fabless Design Houses