Physical Design Technical Lead, ASIC, TPU

About the job

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
• Experience in Python, Tcl, or Perl scripting.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
• Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
• Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
• Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.

Pay

$192,000 - $279,000 (USD) + 20% bonus target + equity + benefits

Schedule

Not specified

Benefits

Not specified