Physical Design Lead Engineer

Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client locations throughout the U.S.

Responsibilities

• Implement complex design in physical design flow from netlist to GDSII.
• Work on TSMC advanced process nodes (3nm or below).
• Handle floor-planning, CTS (Clock Tree Synthesis), and routing using ICC2, Innovus tools related to Cadence and Synopsys.
• Optimize design with multi-corner multi-mode (MCMM) timing constraints.
• Fix setup, hold, transition, capacitance, crosstalk violations, min pulse width (MPW), signal EM (Electromigration), and resolve congestion, short, skew, etc.
• Work on high-speed and complicated clock structure designs with a large number of memories and instances.
• Use PrimeTime to check and debug timing.
• Analyze floorplan to reduce congestion using advanced scripting techniques and generate a robust clock tree by analyzing sync points to achieve low latency and minimal power.
• Perform Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, and Power analysis.
• Control timing budgets between blocks and the top-level chip using timing models such as ETM and ILM.
• Build ECO environments for place and route tools to fix all timing violations.
• Conduct Power Analysis and IR Drop Analysis to meet requirements.
• Perform Physical Verification (PV), Design Rule Check (DRC), Layout Versus Schematic (LVS), Antenna, Electrical Rule Check (ERC), and Design for Manufacturing (DFM).
• Execute logic equivalence check (LEC) for Pre- and Post-Place and Route design.

Requirements

• Bachelor’s degree (or foreign equivalent) in Electronics Engineering or a related field.
• Five (5) years of experience in the job offered or a related position.
• Demonstrable knowledge of:
  • The full Place & Route design flow including logical synthesis, STA, DFT, Placement, Clock Tree Synthesis, and physical verification.
  • Hardening high-speed, low-power CPU designs.
  • Design of large SOC full chip and block-level P&R using advanced process technologies (3nm or below).
  • High-speed interfaces at the chip level.
  • Clock tree creation including sync points and achieving low latency and minimal power.
  • Design with multi-corner multi-mode timing constraints.
  • Static Timing Analysis (STA).
  • Control of timing budgets between blocks and chip using timing models such as ETM and ILM.
  • ECO environments for place and route tools to fix timing violations.
• Travel to unanticipated client locations throughout the U.S., approximately 30%, as required.
• May telecommute from any location within the U.S.

Pay

$130,333 - $160,000

Benefits

• Comprehensive health insurance
• Paid time off
• Retirement plan