Principal NoC IP Micro-Architect

About the role

This role is a highly visible technical leadership role requiring deep expertise in SoC interconnect architectures, NoC fabrics, RTL development, performance modeling, and system-level optimization.

Responsibilities

• Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Creates prototypes, simulates models, and specifies systems requirements.
• Prepares and designs logic diagrams and codes for implementing system design and test specifications.
• Delivers software models for device level bring up, including user visible functionality, timing, and power.
• Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
• Strong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhance the development efficiency.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.

Qualifications

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
• 10 + years of experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis.
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience with the usage of AI with development process for high efficiency development would be a great plus.