Principal NPU Microarchitect

Responsibilities

• Define and evolve the NPU core microarchitecture, including compute datapaths, instruction flow, hardware scheduling strategy, quantization support, and execution efficiency for deep learning inference workloads.
• Architect solutions that map effectively onto Rivian’s custom hardware model, including the processing array, silicon partitioning strategy, and coordination of instruction and data movement across the engine.
• Drive architectural tradeoffs across PPA (Performance, Power, Area), utilization, latency, and scalability.
• Lead the definition of mechanisms for efficient movement of tensor activations, weights, and outputs through on-chip and off-chip memory pathways and high-throughput DMA architecture.
• Partner closely with compiler, model, firmware, RTL design, hardware verification, and SoC teams to ensure ML models are translated into efficient executable flows for the accelerator.

Qualifications

• Deep expertise in computer architecture, logic design, and silicon microarchitecture, with a strong track record of taking complex compute blocks from concept through tape-out and production.
• Strong understanding of machine learning inference hardware components, including custom execution datapath design, hardware-managed scheduling, numerical formats, quantization, and microarchitectural performance optimization.
• Direct experience architecting, modeling, or designing specialized compute engines such as NPUs, TPUs, AI accelerators, vector/SIMD/tensor processors, or systolic arrays.
• Expert knowledge of on-chip memory hierarchy and hardware data movement, including SRAM bank organization, high-throughput DMA engines, multi-buffered structures, bandwidth management, and latency hiding techniques.
• Experience working across the hardware-software boundary, explicitly partnering with compiler teams, runtime development, or ML model deployment teams on hardware-software co-design.
• Proven ability to evaluate architectural tradeoffs using cycle-level, trace-driven, or analytical performance modeling, analysis, and empirical workload characterization.
• Excellent communication skills and the ability to drive technical alignment across RTL design, hardware verification, physical design, firmware, compiler, and product teams.

Preferred Qualifications

• Experience with automotive SoC or safety-critical silicon development (e.g., ISO 26262, ASIL requirements).
• Experience mapping production deep learning workloads—such as Transformers, CNNs, or Large Language Models (LLMs)—onto custom hardware fabrics, particularly in perception and autonomy contexts.
• Familiarity with instruction-driven accelerator architectures, partitioned compute fabrics, and high-efficiency memory orchestration.
• Hands-on experience with hardware modeling frameworks (e.g., SystemC, C++, Python architectural simulators) or pre-silicon emulation.
• Experience defining architecture for systems that must strictly balance throughput, determinism, power efficiency, and silicon-level debuggability.

Pay

The listed base salary range for this role is $218,000 - $312,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.