Principal SoC IP & Interconnect Architect

Ampere is a semiconductor design company leading the future of computing with an innovative approach to CPU design focused on high-performance, energy-efficient AI compute. As part of the Softbank Group, we drive sustainable computing for AI, Cloud, and edge applications.

About the Role

As a Principal SoC IP & Interconnect Architect, you will apply deep technical expertise and architectural leadership to define and integrate advanced SoC and interconnect IP for next-generation Ampere products. This critical role drives the architecture of high-performance I/O and interconnect subsystems, navigating complex system-level requirements and integration tradeoffs.

Responsibilities

• Lead the definition, architecture, and integration of SoC and interconnect IP for next-gen Ampere products.
• Own the end-to-end architecture of one or more I/O and interconnect subsystems, balancing performance, scalability, power, reliability, and platform requirements.
• Drive cross-functional alignment with system architects, design, verification, and software teams to deliver cohesive, production-ready SoC IP solutions.
• Outline subsystem interfaces, integration strategies, and architectural requirements to ensure seamless connectivity across the SoC platform.
• Define subsystem-level SoC architecture in collaboration with CPU and compute-engine teams, aligning with the SoC chassis, global architecture, and integration requirements.
• Influence key technical decisions and resolve complex architecture and integration tradeoffs throughout the product development lifecycle.

Requirements

• 6+ years of proven SoC design or architecture experience.
• Familiar with SoC interconnect and coherent fabric architecture.
• Deep understanding of AMBA-based interconnect protocols (AXI and CHI), and their application in high-performance, cache-coherent SoC designs.
• Knowledge of cache-coherent memory systems, DMA traffic, and interconnect performance tradeoffs.
• Hands-on experience developing architectural performance models for bandwidth, latency, scalability, and workload analysis.
• Experience across the full IP lifecycle, from IP selection and integration through silicon validation, performance debug, and bring-up.

Qualifications

• Additional skills highly desired: Previous RTL/Logic Design or Design Verification Experience; IP Integration: Boot / Reset Flows, Performance Modeling; Power Delivery; Power Management; Clocking; Debug/Trace; Interrupts; RAS.
• BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 8 years of related experience, MS degree & 6 years, or PhD & 3 years.

Pay

The full base pay range for this role is between $182,000 and $273,000, except in the San Francisco Bay Area where the range is between $195,000 and $292,000.

Benefits

• Premium medical, dental, and vision insurance, as well as income protection and a 401K retirement plan.
• Unlimited flextime and 10+ paid holidays for a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks.