Principal Foundry Interface Design Engineer, HBM

About the role

Micron Technology’s HBM Design Architecture team, part of the HBM DRAM Engineering Group, works at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide. In this full‑time onsite position, you will provide critical technology support for the design and development of advanced HBM DRAM products, acting as a bridge between internal design teams, foundries, and technology development groups. Your work will directly impact performance, power efficiency, reliability, and the long‑term HBM roadmap.

Responsibilities

• Foundry Interface and Technology Alignment: Act as the primary technical interface between foundry partners and Micron design organizations; drive closure of design‑process gaps; influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement; define technology requirements for future HBM and custom memory products.
• Circuit Simulation and Analysis: Perform HSPICE simulations for technology evaluation and design optimization; evaluate compact models, PDK SPICE models, and process corners; conduct pre‑layout and post‑layout circuit analysis; support BEOL optimization and routing studies; develop methodologies for evaluating design sensitivity to process variations.
• Test‑Chip and Silicon Validation: Plan and execute technology evaluation test chips; define process monitor structures and benchmark vehicles; analyze post‑silicon data and correlate results with simulations; collaborate with product engineering and foundry/Fab teams on silicon learning and technology qualification.
• PDK and Design Enablement: Evaluate foundry PDKs and IP collateral; support design teams with technology guidelines and best‑known methods; drive creation of design recommendations, analog guidelines, and digital PPA evaluation methodologies; collaborate with CAD teams on flow enablement and validation.
• AI‑Enabled Productivity and Efficiency Improvement: Identify and implement AI‑enabled workflows, automation opportunities, and knowledge‑management practices to improve engineering productivity, decision quality, and execution efficiency across DTCO, foundry interface, PDK evaluation, and design enablement activities.

Minimum Qualifications

• BS, MS, or PhD (or equivalent experience) in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of semiconductor industry experience with a solid grasp of advanced semiconductor technology development.
• Strong understanding of advanced CMOS technology nodes, FinFET devices, and process integration.
• Hands‑on experience with HSPICE simulations, device characterization, standard cell benchmarking, PPA analysis, parasitic extraction, and physical verification.
• Experience driving AI‑enabled engineering practices and automation to improve DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and knowledge sharing across design teams.

Preferred Qualifications

• Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
• Experience with memory products including DRAM, HBM, or SRAM.
• Knowledge of TSV technologies, advanced packaging, reliability modeling and aging simulations, advanced BEOL technologies, and PDK development and validation.
• Ability to utilize AI tools to summarize, analyze, and extract insights from PDK documentation, design rule manuals, reliability reports, foundry collateral, and silicon characterization data.
• Experience leading technology pathfinding and node selection activities.

Pay

The US base salary range for this full‑time position is $146,000 – $297,000 per year. Additional compensation may include bonuses, equity, and benefits. Salary within the range is determined by location, knowledge, skills, experience, tenure, and relevant education or training.

Benefits

• Medical, dental, and vision plans with a choice of options to suit family needs and budget.
• Income protection programs for illness or injury and paid family leave.
• Robust paid time‑off program and paid holidays.
• Access to a Benefits Guide with detailed information on all programs.