Custom HBM Architecture and Design Engineer

About the role

As a Custom HBM Architecture and Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the architecture, design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, design, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role for candidates passionate about architecture, RTL build, IP integration, debugging, and pre/post-silicon support.

Responsibilities

• Analyze hardware and software interaction at the system level to identify bottlenecks in existing AI/ML workloads and HBM-based hardware.
• Drive future HBM architecture, design, and technology to address bottlenecks, including implementing proof of concept designs.
• Architect, design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die.
• Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization.
• Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic).
• Translate architectural and micro‑architectural specifications into high‑quality RTL implementations.
• Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Minimum Qualifications

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field, with a minimum of 10 years of experience in a related field.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL‑to‑GDS flow, including synthesis, static timing analysis, and develop sign‑off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

Preferred Qualifications

• Experience with HBM, DRAM, or memory‑centric SoC designs.
• Familiarity with high‑speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).

Pay

$165,000.00 – $329,000.00 a year