Staff Foundry Interface Design Engineer- HBM - TPG

Responsibilities

• Analyze advanced foundry PDKs (FinFET and GAA) and develop design guidelines for power, performance, area, and reliability
• Provide technical support for PDK-related issues and collaborate with CAD teams, tool vendors, and foundries
• Drive design-technology co-optimization for future HBM base die architectures, including standard cells and BEOL options
• Define reliability specifications and support yield, reliability, and technology qualification efforts
• Explore and evaluate new architectures for future HBM products through detailed technical feasibility analysis

Requirements

• Bachelor’s degree in Electrical Engineering or related field with 4+ years of relevant industry experience
• Hands-on experience working with foundry technology PDKs at advanced CMOS nodes
• Experience with EDA tools, CMOS circuit design, parasitic extraction, and circuit simulation
• Solid understanding of advanced CMOS device physics, including FinFET and GAA architectures

Qualifications

• Master’s degree or higher in Electrical Engineering or a related technical field
• Experience with reliability and aging models for advanced CMOS technologies
• Strong automation and scripting skills using Python or similar languages
• Background in HBM, DRAM, or high-speed memory design and validation

Skills

Not specified

Benefits

Not specified

Pay

$175,000.00 - $297,000.00 a year

Schedule

Full-time onsite