Principal Engineer - FPGA/ASIC Design

About the role

This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challenges in the industry while being part of a global, multi-disciplinary team. In this role, you will design, verify, integrate, and test FPGA/ASIC solutions, which will be integrated in current and future Rolls-Royce engine control system products.

Responsibilities

• Design, verify, integrate, and test FPGA/ASIC solutions, which will be integrated in current and future Rolls-Royce engine control system products.
• Develop FPGA/ASIC architectures, code, run simulations, synthesize, create test benches, and prepare documentation to be reviewed by certification authorities.
• Participate in all phases of project, to produce detailed design documentation, verification plans and reports.
• Design and develop all custom digital devices (ASIC or FPGA), to support RR electronic engine control units.
• Verify complex products that use FPGAs and/or ASICs to DO-254.
• Validate the FPGA hardware in the lab using test equipment (oscilloscopes, logic analyzers) and debug tools (e.g ILA, JTAG).
• Script with languages such as TCL, Python, Shell scripts.
• Work with Windows and Linux development environment.
• Experience in version control, such as Git, SVN.
• Develop model-based systems with digital engineering toolsets (MATLAB, Simulink and/or similar).
• Knowledge of systems engineering, and robust design tools and techniques coupled with the latest model-centric development approaches.
• Use Cameo Systems Modeler (MagicDraw) or similar SysML modelling software.

Requirements

• Bachelor's degree in Electronics Engineering and/or Computer Engineering with 5+ years of experience, OR Master's degree in Electronics Engineering and/or Computer Engineering with 3+ years of experience, OR PhD in Electronics Engineering and/or Computer Engineering.

Qualifications

• Validate the FPGA hardware in the lab using test equipment (oscilloscopes, logic analyzers) and debug tools (e.g ILA, JTAG).
• Able to work with Windows and Linux development environment.
• Experience in scripting with languages such as TCL, Python, Shell scripts.
• Experience of Actel & Xilinx tool flows to implement complete designs.
• Development of model-based systems with digital engineering toolsets (MATLAB, Simulink and/or similar).
• Knowledge of systems engineering, and robust design tools and techniques coupled with the latest model-centric development approaches.
• Use Cameo Systems Modeler (MagicDraw) or similar SysML modelling software.

Skills

• Expertise achieving timing closure on FPGA designs and generating test benches.
• Evaluate the process flow including but not limited to high level design, synthesis, place and route, timing constraints and power utilization.

Benefits

• Excellent development opportunities.
• A competitive salary.
• Exceptional benefits including bonus, employee support assistance and employee discounts.
• Relocation assistance is available for this position.

Pay

$113,179 - $183,916 Annually

Schedule

Hybrid Work Schedule