Principal Engineer- Design (FPGA)

About the Role

Microchip’s NCS Team is seeking an experienced FPGA Design Engineer to support PHY (Physical Layer) development and system-level solutions for our next generation of USB and Ethernet products. The role involves working closely with digital, analog, and software engineers to develop, integrate, and validate FPGA-based platforms supporting mixed-signal IP and SoC products. The candidate must be located in the Chandler Design Center.

Responsibilities

• Develop, integrate, and validate FPGA-based platforms for mixed-signal IP and SoC products.
• Design and implement RTL coding, simulation, synthesis, and hardware implementation for FPGA solutions.
• Create self-checking testbenches and perform functional simulation and debug using tools such as QuestaSim/ModelSim.
• Perform FPGA synthesis, implementation, timing analysis, and place-and-route using vendor tools like AMD/Xilinx Vivado.
• Define and analyze timing constraints for systems containing multiple clock domains.
• Optimize FPGA designs for performance, area/resource utilization, and target clock frequencies.
• Conduct FPGA system integration and board-level bring-up, including debugging on physical circuit cards.
• Use laboratory debug equipment such as oscilloscopes, logic analyzers, protocol analyzers, and FPGA embedded logic-debug tools.
• Collaborate with hardware, firmware, software, ASIC, analog, verification, and validation teams during system integration and lab bring-up.
• Provide clear design documentation, including requirements, FPGA architecture, block diagrams, and interface control documents.
• Automate FPGA build, simulation, synthesis, and implementation flows using scripting languages (TCL, Python, Perl) or programming languages (C++, RUST).
• Utilize revision-control systems such as Perforce, Git, or DesignSync for tagging, branching, configuration management, and release methodologies.

Requirements

• 10+ years of experience in FPGA and/or digital design.
• Strong proficiency in Verilog and/or SystemVerilog for synthesizable RTL design.
• Solid understanding of digital design fundamentals: state machines, datapaths, pipelines, clocking, resets, FIFOs, memories, and interface logic.
• Experience with USB and Ethernet PHY architectures and protocols (strong plus).
• Strong verbal and written communication skills for technical discussions, design reviews, and documentation.

Skills

• RTL coding, simulation, synthesis, and hardware implementation.
• FPGA vendor tools (AMD/Xilinx Vivado).
• Timing constraint definition and multi-clock domain design.
• Laboratory debug equipment (oscilloscopes, logic analyzers, protocol analyzers).
• Scripting languages (TCL, Python, Perl) and programming languages (C++, RUST).
• Revision-control systems (Perforce, Git, DesignSync).

Benefits

Microchip Technology Inc. offers a culture of trust, empowerment, respect, diversity, and communication. Employees benefit from:

• Nationally-recognized Leadership Passage Programs with over a thousand participants annually.
• Career growth and stability in a multi-billion-dollar global organization.
• Award-winning workplace excellence and diversity initiatives (Aggregate System).
• Record revenue and over 30 years of quarterly profitability.

Travel

0% - 25% travel time.

Physical Requirements

• 80% sitting, 10% standing, 10% walking.
• Requires feeling, hearing, seeing, and talking.
• Involves working both alone and around others.