Principal Engineer, Design Verification

Key Responsibilities

• Define and implement the DV strategy for the group, ensuring alignment with business objectives and product roadmaps
• Develop comprehensive DV plans for multiple projects as required
• Drive adoption of state-of-the-art DV methodologies including advanced UVM architectures, formal verification, portable stimulus (PSS), and AI/ML-assisted verification techniques
• Establish verification metrics, KPIs, and quality gates to measure verification progress and coverage closure
• Lead and mentor a small team of design verification engineers, providing technical guidance and career development support
• Conduct code reviews, testbench architecture reviews, and methodology assessments
• Collaborate on recruiting, interviewing, and onboarding new verification talent
• Architect scalable, reusable verification infrastructure across multiple projects and product generations
• Drive evaluation and adoption of new EDA tools, verification IP, and emerging methodologies
• Lead development of advanced testbench components including UVM environments, formal verification approaches, and mixed-signal verification solutions
• Support all projects across the portfolio with DV planning, execution oversight, and technical problem-solving
• Interface with product engineering, applications, and silicon validation teams
• Represent the verification team in project reviews, design reviews, and executive briefings
• Develop and document best practices, guidelines, and playbooks for the verification organization
• Stay current with industry trends and drive adoption of relevant innovations

Minimum Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering
• 10+ years of hands-on experience in SystemVerilog/UVM-based verification
• 3+ years of technical leadership experience, including mentoring engineers, leading verification efforts on complex projects, or managing small teams
• Demonstrated experience architecting verification environments for complex mixed-signal SoCs or power management ICs
• Expert-level proficiency in EDA tools and automation (Python, TCL, Perl, Shell) for building verification infrastructure and flows
• Experience with formal verification methodologies and tools (JasperGold, VC Formal, or equivalent)
• Strong understanding of coverage-driven verification, including functional coverage modeling and closure strategies
• Excellent communication skills with the ability to present technical content to diverse audiences, including executives

Preferred Qualifications

• Experience with portable stimulus standard (PSS) and graph-based verification approaches
• Deep knowledge of analog/mixed-signal verification techniques including SV-RNM modeling
• Experience with verification of ARM/RISC-V based sub-systems or complex SoCs
• Expertise in power management IC verification, including multiphase DC-DC controllers, voltage regulators, and power sequencing
• Knowledge of emulation and FPGA prototyping methodologies for early software enablement RTL design experience providing strong design-for-verification perspective
• Experience building and scaling verification teams or capabilities
• Track record of driving process improvements that measurably improved verification quality or efficiency
• AI/ML tools for verification – keen interest and experience leveraging AI for coverage closure, test generation, debug, or productivity improvements
• Proficiency with multiple verification platforms (Cadence, Synopsys, Mentor/Siemens)
• Experience with continuous integration/continuous verification (CI/CV) pipelines
• Familiarity with cloud-based verification and distributed simulation/regression management
• Version control expertise (Git, Perforce) and collaborative development workflows
• Verilog, C/C++, SystemC for modeling and verification
• Strong analytical and debug skills with ability to drive complex issues to resolution