Principal Design Verification Engineer

About the role

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We are energized by our mission to reduce the barrier of entry for content creation and consumption.

Responsibilities

• Define and drive end-to-end verification strategy (block → subsystem → full-chip)
• Build, mentor, and scale a high-performing DV team
• Establish verification plans, milestones, and coverage goals
• Drive alignment across architecture, RTL, and physical design teams
• Lead development of UVM-based verification environments
• Define testbench architecture, stimulus strategy, and reusable components
• Drive functional, code, and assertion coverage closure
• Oversee regression infrastructure, debug, and signoff criteria
• Drive GLS (Gate-Level Simulation) with SDF annotation and timing-aware debug
• Manage low-power verification (UPF/CPF) and power-aware simulation
• Oversee formal verification, linting, CDC/RDC analysis
• Ensure robust reset, clocking, and cross-domain verification
• Work with RTL teams on design-for-verification (DFV) improvements
• Collaborate with PD teams on timing-related verification issues
• Support post-silicon bring-up and debug
• Interface with customers/partners on verification readiness and quality

Requirements

• Bachelor’s/Master’s degree in Electrical Engineering or related field
• 12–15 years of experience in ASIC/SoC design verification
• Proven experience leading verification teams and delivering multiple tapeouts
• Strong expertise in:
• SystemVerilog and UVM methodology
• Functional coverage, assertions (SVA), and constrained-random verification
• Debugging complex SoC-level issues
• Hands-on experience with industry-standard tools such as: Synopsys VCS / Cadence Xcelium, Synopsys Verdi
• Strong understanding of:
• Clock/reset domain crossings (CDC/RDC)
• Low-power verification methodologies
• Gate-level simulation and SDF annotation
• Excellent leadership, communication, and problem-solving skills

Qualifications

• Expertise in CPU/GPU/AI/Networking SoCs
• Experience in GLS debug (X-propagation, SDF issues, timing failures)
• Familiarity with emulation platforms (e.g., Synopsys ZeBu)
• Experience with post-silicon validation and bring-up
• Knowledge of performance verification and system-level validation
• Strong scripting skills (Python/TCL) for automation and regression scaling

Skills

• SystemVerilog and UVM methodology
• Functional coverage, assertions (SVA), and constrained-random verification
• Debugging complex SoC-level issues
• Hands-on experience with industry-standard tools such as: Synopsys VCS / Cadence Xcelium, Synopsys Verdi
• Strong understanding of:
• Clock/reset domain crossings (CDC/RDC)
• Low-power verification methodologies
• Gate-level simulation and SDF annotation

Benefits

• Medical, Dental, & Vision - 100% covered premiums
• Equity - Stock Options
• 401(k) match
• WFH

Pay

Compensation Range: $250,000–$280,000 per year (California).