Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

About the Role

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOC) to systems of chips. Marvell's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. This role will contribute to the development of timing constraints, STA signoff flows, and methodologies for both SOC and block levels in advanced technology nodes.

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to understand design requirements, analyze timing complexities, and develop consolidated timing modes and constraints for STA signoff.
• Own and contribute to various STA-related tasks such as timing ECOs for blocks and SoCs, developing custom scripts to create histograms, and STA flow management.
• Perform static timing analysis (STA) using industry-standard tools (e.g., Primetime).
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Resolve or find workarounds for tool issues, independently or working with EDA tool vendors.
• Conduct post-route timing checks and quality of results (QoR) analysis.
• Automate STA-related processes/flows using scripting languages such as Tcl or Python.
• Create QoR dashboards and histograms for STA runs across all modes.
• Ensure compliance with timing signoff checklists and criteria.
• Document best practices and lessons learned to drive continuous improvements in future projects.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 10-15 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience.
• Minimum of 5 years of industry experience in ASIC timing and STA.
• Strong understanding of ASIC design flows, from RTL to GDSII.
• Knowledge and hands-on experience with STA methodologies and implementation.
• Proficiency in using STA tools and scripting languages (e.g., Tcl, Perl).
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Strong understanding of timing constraint development for hierarchical designs, timing ECO creation, and final timing signoff.
• Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure.
• Proven track record of delivering successful designs on time and meeting performance, power, and area goals.
• Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues.
• Strong communication and collaboration skills to work effectively within cross-functional teams.

Pay

Expected Base Pay Range (USD): $160,400 - $237,320 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.