ASIC Design STA Engineer

About the role

Amd is seeking an ASIC Design STA Engineer to contribute to the development of large SoCs featuring multiple physical blocks and over 300 clock domains. The candidate will be responsible for building and verifying timing constraints for intricate SoC designs.

Responsibilities

• Develop complex multi-mode/multi-corner timing constraints compatible for RTL and signoff
• Lead efforts to maintain RTL quality metrics in complex, hierarchical designs while automating the process for increased efficiency
• Implement pre-route timing checks and QoR clean-up to eliminate timing constraint issues and ensure a quality handoff for STA checks
• Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) workflows

Requirements

• SDC expertise, EDA tool proficiency, and TCL-based scripting abilities
• Experience with EDA tools enabling RTL quality checks
• Experience with building timing constraints for IPs, blocks, and full-chip implementation in both flat/hierarchical flows
• Experience analyzing timing reports and identifying both design and constraint-related issues
• Ability to multitask, grasp new flows/tools/ideas
• Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
• Strong analytical and problem-solving skills

Qualifications

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering or a related field

Benefits

The benefits offered are described: AMD benefits at a glance.