Principal Electrical Engineer-FPGA Verification

About the role

The Radar Digital Products (RDP) Department at Raytheon is seeking an experienced Principal level Electrical Engineer to verify FPGA based designs for control and/or signal processing radar applications. This position can be for the Tewksbury, MA location or the Marlborough, MA location.

Responsibilities

• Own or contribute to the successful completion of FPGA-based designs, on time and on budget
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM
• Create complete documentation including verification plan and report
• Demonstrate self-motivation, with little supervision required
• Work cooperatively with systems, hardware, software engineers, and program management to ensure product success
• Support internal and external technical reviews

Qualifications

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience
• Strong proficiency in SystemVerilog for both design and verification (interfaces, clocking blocks, assertions)
• Hands-on experience building UVM-based testbenches from scratch, including env, agent, scoreboard, and coverage components
• Solid understanding of constrained-random verification and functional coverage methodology
• Familiarity with AXI, PCIe, Ethernet, DDR protocols. Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium)
• Experience with regression management and debug of complex, intermittent failures
• Experience developing and maintaining verification plans tied to design specifications and coverage closure criteria
• Experience with version control systems (e.g., Git, ClearCase, SVN) in a team-based development environment

Qualifications We Value

• Proficiency with Git. Branching strategies, pull requests, and collaborative workflows
• Experience with UVMF (UVM Framework) for structured, reusable testbench development
• Familiarity with Vivado and Quartus FPGA simulation flows
• Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling
• Experience designing FPGAs using VHDL
• Familiarity with SLURM workload manager for job scheduling and compute cluster resource management
• Prior experience mentoring junior verification engineers

What We Offer

• Safe, Trust, Respect, Accountability, Collaboration and Innovation
• Relocation eligibility
• Competitive salary range of $107,500 - $204,500
• Benefits including medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays
• Annual short-term and/or long-term incentive compensation programs