FPGA Design Verification Engineer

Role Description

Who We Are
Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world. UST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries. Our entrepreneurial teams are empowered to innovate, act nimbly, and create a lasting and sustainable impact for our clients, their customers, and the communities in which we live. With us, you’ll create a boundless impact that transforms your career—and the lives of people across the world.

Opportunity

Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, System Verilog, RTL). Write and debug test cases to verify functionality, performance, and corner cases. Identify and debug issues, working closely with design engineers to resolve them. Participate in design reviews and contribute to the overall verification strategy. Stay up-to-date with the latest verification methodologies and tools.

Qualification

• Strong understanding of FPGA, ASIC, RTL design principles and architectures.
• Proficiency in System Verilog and UVM verification methodology.
• Experience with Linux operating system.
• Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps).
• Experience with high-speed I/O design and protocols.
• Knowledge of PCIe, I2C, SPI, etc.
• Hands on experience with lab debugging tools including logic analyzer, oscilloscope, and JTAG.
• Excellent debugging and problem-solving skills.
• Strong communication and collaboration skills.

Desired Skills

• Experience in hardware validation or embedded test automation.
• Experience with scripting languages (e.g., Python, Perl).

Compensation and Benefits

Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.

Role Location: California
Cash Range: $101,000-$152,000

Benefits
Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits.

Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines.

Benefits offerings vary in Puerto Rico.

Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance. Part-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year). All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.