Principal ASIC Test Development Engineer

About the role

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Job Description

• Individual contributor role responsible for testability solutions of ASICs, memory, and 2.5D SiPs for Juniper’s product development and manufacturing.
• Includes both structured ATE-level test as well as system-level/mission-mode (functional) environments.
• Develops test strategy and DFT (Design-for-Test) solutions for ASICs and 2.5D SiP that supports high test coverage requirements of components and systems.
• Works between HW Eng development teams and Supplier Development Teams.
• Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in diagnostics, and implement in manufacturing tests.
• Develops innovative DFT IP in collaboration with cross-functional teams inside and outside the company.
• Engages in test standard working groups, such as IEEE 1149, 1687, P1838, JC-42 Solid State Memories.
• Trusted advisor on ASIC testability to Juniper teams including ASIC frontend, physical design, DFT, system software, diagnostics, hardware and manufacturing test teams.
• The influence occurs from the beginning (ASIC kick-off) to production release.
• Recognizes and solves structural vs functional test coverage gaps, as well as weaving in new fault models for advanced semiconductor technology nodes.
• Works closely with component engineers to resolve high DPPM ASIC issues at EMS partner sites.
• Able to independently solve NTF (No-Trouble-Found) supplier issues, via creating unique ATE-level tests to solve such issues, per strong knowledge of a chip’s design.
• Responsible for influencing supplier testing to implement Juniper-favorable manufacturability modes at their production test.

Qualifications

• Demonstrated Principal or Distinguished Engineer expertise.
• A minimum of 15+ years of experience in testability and DFT area for ASICs, memories, and 2.5D SiPs.
• Excellent knowledge of state-of-the-art DFT techniques in MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and 1687.
• Strong working level experiences on ASIC DFT implementation, post-silicon validation, debug, and diagnostic integration.
• Exposure to various semiconductor test challenges and solutions for high-performance ASICs, TSV, HBM (High Bandwidth Memory) DRAM, 2.5D, and 3D ICs.
• Broad experiences with ASIC suppliers, IP/EDA vendors, 2.5D SiP ecosystems partners, and contract manufacturers.
• Excellent communication, collaboration and program management skill set. Able to independently influence others.

Education

• BS, MS or PhD Electrical Engineering

What We Can Offer You

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Information about employee benefits offered in the US

Information about employee benefits offered in the US

HPE is an Equal Employment Opportunity/ Veterans/ Individual with Disabilities employer.

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