Principal Application Engineer- Timing Sign Off

About the Role

Support customer tapeouts for leading-edge designs, diagnosing timing, power, and signoff issues in PrimeTime, PrimeShield, PrimeClosure, and PrimePower under real schedule pressure. You will work with the most advanced chip designs in the world, and what you enable will directly determine whether those chips make it to market.

Responsibilities

• Deploy newly developed signoff features with customers, working through beta testing, adoption blockers, and methodology integration in live design environments.
• Evaluate customer requirements and translate them into actionable enhancement requests for the product development team, backed by real use cases and data.
• Build and deliver technical training content, demos, and methodology documentation that help customers and internal teams use signoff tools correctly and confidently.
• Replicate, debug, and escalate product issues, working across engineering, R&D, and account teams to resolve problems that affect customer schedules.
• Mentor applications engineers and customer design teams on timing signoff best practices, corner case handling, and flow optimization.
• Align technical enablement plans with account strategy, ensuring that the right customers get the right support at the right stage of their design cycle.

Impact

• Enable customers to tape out complex, leading-edge designs on schedule by solving signoff problems that would otherwise delay or derail their projects.
• Influence the development roadmap for Synopsys signoff tools by surfacing real customer pain points and advocating for the features that matter most.
• Accelerate adoption of new signoff capabilities across the customer base, turning beta features into production workflows that improve design quality and turnaround time.
• Reduce escalations and support load by creating training materials and methodology guides that help customers solve problems independently.
• Strengthen customer relationships and renewals by being the engineer they trust when the stakes are highest.
• Raise the technical capability of the broader applications team through mentorship, knowledge sharing, and methodology leadership.
• Shape how the semiconductor industry approaches timing signoff for the next generation of AI, 5G, automotive, and high-performance computing designs.

Requirements

• Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field.
• 10+ years of hands-on experience with timing analysis and signoff tools, flows, and methodologies in a customer-facing or product development role.
• Deep working knowledge of PrimeTime, and direct experience with at least two of the following: PrimeShield, PrimeClosure, PrimePower.
• Demonstrated ability to debug complex signoff issues under tapeout pressure and propose solutions that balance accuracy, runtime, and methodology constraints.
• Strong understanding of static timing analysis fundamentals, including multi-mode multi-corner analysis, OCV, AOCV, path-based analysis, and signoff closure techniques.
• Experience with adjacent tools like StarRC, RedHawk-SC, Spice, Hspice, or PrimeSim is a strong plus.
• Proven ability to work effectively across global teams, including product engineering, account management, and customer design teams in different time zones.

Qualities

• You can walk into a customer war room during a tapeout crisis, assess the situation, and explain what needs to happen next in a way that calms the room instead of adding to the chaos.
• You know when to escalate a problem to R&D and when to solve it with a methodology change, and you do not confuse the two.
• You are comfortable saying "I don't know, but I will find out" and then actually finding out, usually faster than anyone expected.
• You can present a technical concept to a room of senior engineers and make it clear without dumbing it down, and you can do the same thing in a slide deck or a two-sentence Slack message.
• You care about making other engineers better, whether that is a junior AE learning signoff or a customer engineer trying to close timing on a hard block.
• You treat customer schedules like they matter because you know they do, and you organize your work accordingly.

About the Team

You will be part of the Silicon Design and Signoff Applications Engineering team, supporting customers who are building the most advanced chips in the world using Synopsys timing signoff tools. This is a global team that works closely with product development, sales, and customer design teams to deploy new capabilities, solve hard problems, and shape the future of signoff methodology. The work is technical, high stakes, and directly tied to whether customers can ship their products on time.