Principal Analog Design Engineer, HBM

About the role

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed‑signal IPs for High Bandwidth Memory (HBM) products. This role is critical in developing and integrating high‑performance analog subsystems within the HBM logic die, enabling industry‑leading bandwidth, power efficiency, and reliability. As a principal engineer, you will provide deep technical leadership across analog design, IP integration, system alignment, and silicon execution, driving end‑to‑end success of HBM solutions.

Responsibilities

• Lead the design and own critical HBM analog circuits, including high‑speed transmitters and receivers.
• Clock generation and distribution (PLLs, DLLs, CDRs) and SerDes‑related analog blocks.
• Biasing, reference, and calibration circuits.
• Power delivery and regulation circuits (LDOs, regulators).
• Define and manage IP interfaces, power domains, clocking schemes, and reset strategies across subsystems.
• Perform detailed pre‑layout and post‑layout simulations.
• Conduct PVT, Monte Carlo, mismatch, and aging analyses.
• Work closely with layout engineers to define floorplanning and symmetry requirements, ensure matching, shielding, and EM/IR compliance.
• Review and sign off on analog layouts.
• Drive layout‑aware design optimizations for advanced nodes.
• Define best practices for analog design, documentation, and reuse.
• Collaborate across analog, digital, system, packaging, and test teams.

Minimum Qualifications

• MS or PhD in Electrical Engineering or related field.
• ~10–15+ years of experience in analog/mixed‑signal IC design.
• Proven expertise in high‑speed interface design, clocking circuits (PLL/DLL/CDR), and power management circuits.
• Strong experience in analog IP integration at subsystem or SoC level.
• Proficiency with SPICE simulation, extraction, and modeling.
• Experience with silicon bring‑up and lab validation.
• Deep understanding of advanced CMOS processes, noise, jitter, SI/PI, and cross‑domain coupling effects.

Preferred Qualifications

• Deep knowledge of DRAM sub‑system architecture, specification, operation, or design.
• Understanding of physical layout & circuit floor planning.
• Excellent problem‑solving and analytical skills.

Benefits

• Choice of medical, dental, and vision plans in all locations.
• Benefit programs that protect income if unable to work due to illness or injury.
• Paid family leave.
• Robust paid time‑off program and paid holidays.
• Additional information available in the Benefits Guide on micron.com/careers/benefits.