Principal AI Accelerator Architect
- . Items:
- Analyze AI workloads, kernels and system bottlenecks to identify high-value architectural opportunities.
- Quantify feature value using targeted performance models, workload studies and representative application scenarios.
- Translate architectural ideas into concrete microarchitecture, including datapaths, control, memory behavior, data movement and interfaces.
- Evaluate interactions with the compiler, runtime, programming model and performance-critical kernels.
- Develop, or partner with implementation teams to develop, targeted prototypes, RTL experiments, synthesis studies or analytical models to validate feasibility and estimate power, performance and area.
- Explore architectural alternatives and clearly articulate their benefits, costs, risks and implementation trade-offs.
- Write architectural and microarchitectural specifications that enable RTL, verification, compiler, kernel and system teams to execute.
- Lead cross-functional technical reviews and drive decisions from initial proposal through implementation handoff.
- Partner with implementation teams during development to preserve the architectural intent and resolve issues that emerge.
Requirements/Qualifications/Skills: "What We’re Looking For" list:
- 10+ years of experience in computer architecture, microarchitecture or processor development, including work with CPUs, GPUs, AI accelerators or other high-performance processors.
- Deep understanding of computer architecture and microarchitecture.
- A track record of taking architectural features from workload need or initial concept through microarchitecture definition and implementation.
- Strong quantitative judgment, including the ability to evaluate performance benefits against power, area, complexity and programmability costs.
- Experience using targeted hardware performance models and architecture-exploration tools to evaluate specific features, using Python, C++ or similar environments.
- Ability to reason across workloads, kernels, memory systems, interconnects and compute pipelines.
- Working knowledge of RTL, synthesis, timing, power and physical-design considerations sufficient to establish implementation feasibility.
- Experience collaborating closely with RTL, verification, physical-design, compiler, kernel and system-software teams.
- Strong written and verbal communication skills, including the ability to make and defend consequential architectural decisions.
- MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or equivalent practical experience.
Then "Particularly Relevant Experience" bullet list:
- Architecture or microarchitecture development for machine-learning accelerators, GPUs, CPUs, vector processors or network processors.
- Transformer inference or training, including attention, matrix and vector operations, collectives, sparsity, quantization or mixture-of-experts workloads.
- Memory hierarchy, on-chip networks, DMA engines, distributed compute or large-scale accelerator systems.
- Kernel development, compiler interaction or performance optimization close to the hardware.
"Role Focus" paragraph: "This is an architecture role with hands-on feasibility work. You may develop targeted RTL, synthesis or modeling experiments to answer specific architectural questions, but the position is not centered on production RTL implementation, block-level design ownership or ownership of the broader performance-modeling infrastructure. The central responsibility is to ensure that proposed features are valuable, programmable, implementable and ready for execution."
Pay: "The base salary range for this position is $200,000 to $300,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications."
Benefits: Not explicit. There's a "Why Join Cerebras" section with bullet points: Build a breakthrough AI platform beyond the constraints of the GPU. Publish and open source their cutting-edge AI research. Work on one of the fastest AI supercomputers in the world. Enjoy job stability with startup vitality. Our simple, non-corporate work culture that respects individual beliefs. Those could be considered Benefits. The instruction: include Benefits section only if posting actually states them. This "Why Join Cerebras" is basically benefits/perks. So we can include Benefits section with those items.
Schedule: Not mentioned.
We must not include Job ID etc.
We must not repeat job title as heading.
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for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). It suggests we can use those headings if we have content. We can choose to include only those with real content. We have content for About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay. Schedule none. We need to decide what goes where. Let's map: About the role: introductory paragraphs describing company and role. Responsibilities: "What You’ll Do" list. Requirements: maybe the core requirements: 10+ years experience, deep understanding, track record, strong quantitative judgment, experience with models/tools, ability to reason across..., working knowledge of RTL..., experience collaborating..., strong communication, MS/PhD. Qualifications: "Particularly Relevant Experience" list. Skills: maybe the communication and collaboration skills? But those already in requirements. Could treat Skills as the "Strong written and verbal communication skills" etc. But we already have communication in requirements. Might be redundant. Perhaps we can put Skills as the "Ability to reason across workloads..." etc. But that's also in requirements. Given risk of thin sections, maybe combine Requirements and Qualifications into one section called "Requirements". But the instruction says we can use those headings; it's not mandatory to use all. It says "Use
for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule)." It implies we can use those headings if appropriate. It doesn't say we must use each. So we could have sections: About the role, Responsibilities, Requirements, Benefits, Pay. And put qualifications/skills inside Requirements. But we have "Particularly Relevant Experience" which is definitely qualifications. Could be under Requirements as well. Thus we can have: - About the role (prose) - Responsibilities (ul) - Requirements (ul) combining the bullet lists from "What We’re Looking For" and "Particularly Relevant Experience" - Benefits (ul) from "Why Join Cerebras" - Pay (prose) salary range. We must not include Schedule. Now we need to ensure we preserve all substantive info. Let's extract all prose bits. About the role prose: combine the introductory paragraphs up to "You will own architectural features from initial insight through a well-grounded proposal that is ready for implementation." Also maybe include the sentence "Principal AI Accelerator Architect Our architecture removes many of the constraints..." Actually that's part of role description. Let's capture: "Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Principal AI Accelerator Architect Our architecture removes many of the constraints imposed by conventional collections of packaged processors and creates a fundamentally different design space spanning compute, memory, communication, programmability and system scaling. We are looking for an experienced architect to conceive and drive new capabilities for our next-generation AI accelerators. This is an end-to-end architecture role: you will identify opportunities from important AI workloads, quantify their performance and efficiency value, develop the microarchitecture and establish implementation feasibility across hardware and software. You will own architectural features from initial insight through a well-grounded proposal that is ready for implementation." We need to ensure no duplication. Responsibilities list: as above. Requirements list: combine: From "What We’re Looking For": - 10+ years of experience in computer architecture, microarchitecture or processor development, including work with CPUs, GPUs, AI accelerators or other high-performance processors. - Deep understanding of computer architecture and microarchitecture. - A track record of taking architectural features from workload need or initial concept through microarchitecture definition and implementation. - Strong quantitative judgment, including the ability to evaluate performance benefits against power, area, complexity and programmability costs. - Experience using targeted hardware performance models and architecture-exploration tools to evaluate specific features, using Python, C++ or similar environments. - Ability to reason across workloads, kernels, memory systems, interconnects and compute pipelines. - Working knowledge of RTL, synthesis, timing, power and physical-design considerations sufficient to establish implementation feasibility. - Experience collaborating closely with RTL, verification, physical-design, compiler, kernel and system-software teams. - Strong written and verbal communication skills, including the ability to make and defend consequential architectural decisions. - MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or equivalent practical experience. From "Particularly Relevant Experience": - Architecture or microarchitecture development for machine-learning accelerators, GPUs, CPUs, vector processors or network processors. - Transformer inference or training, including attention, matrix and vector operations, collectives, sparsity, quantization or mixture-of-experts workloads. - Memory hierarchy, on-chip networks, DMA engines, distributed compute
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