Principal AI Accelerator Architect Lead

About the role

Principal AI Accelerator Architect Lead
Boston, MA; San Jose, CA
Role Summary: ADI is seeking a Technology Expert in Analog and Digital AI Accelerators to define and develop a fundamentally innovative approach to artificial intelligence compute, characterized by ultra-low power consumption and deep integration within silicon.

Key Responsibilities

• Translate product requirements, including functions and workloads, into end-to-end system architectures, producing well-defined specifications for IP blocks, processors, firmware, memory subsystems, and AI compute engines.
• Explore new representations of intelligence that go beyond conventional digital AI models and architectures.
• Bridge the gap between academic research and real-world deployment, ensuring ideas withstand contact with physical constraints such as noise, power, variability, node scalability, and manufacturability.
• Lead the architecture exploration and collaborate with the modeling team to drive insights and breakthroughs.
• Define detailed hardware block specifications and interfaces, contributing to modeling and, when appropriate, RTL development.
• Collaborate across architecture, design, verification, firmware, and physical design teams to ensure architectural intent is realized.
• Provide technical leadership and mentorship, influencing architecture decisions across multiple projects and SoC generations.

Minimum Qualifications

• PhD or Master’s degree in Computer Engineering, Electrical Engineering, or a related technical field.
• 10 or more years of practical experience in digital and analog AI Accelerator systems architecture for Physical AI or embedded intelligent platforms, robotics/drones / AV systems.
• Hands-on experience with digital signal processing and both analog and digital neural-network compute architectures.
• Hands-on experience on how to map AI workloads and pipeline into compute requirements.
• Experience in leadership and management roles.
• Proven ASIC design expertise, encompassing high-speed and low-power RTL development, integrating SystemVerilog for analog compute representation, as well as familiarity with physical design flows and constraints.
• Strong expertise in SystemC modeling and virtual prototyping, with demonstrated ability to build and analyze complex system-level models.
• Deep understanding of processor architecture and design, including datapaths, memory hierarchies, interconnects, peripherals, and chip-level interfaces.
• Proficiency with advanced verification methodologies, including UVM, SystemVerilog, SystemC, constrained-random testing, functional coverage, and assertion-based verification.
• Strong programming skills in C and additional languages commonly used for modeling, simulation, or design.
• Excellent written and verbal communication skills.
• Demonstrated technical leadership, curiosity, and a strong work ethic.