Physical Design Methodology Engineer

About the role

Advanced Design and Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tier0/tier1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mm Wave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis are conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost.

Responsibilities

• Create methodologies, models, and flows for advanced design rules for a specific process node and characterize those models through silicon validation.
• Ensure IP and SoC design meets requirements and standards for a specific manufacturing process technology.
• Identify ways to optimize silicon designs by evaluating device performance over a range of operating conditions.
• Resolve prototype issues and determine whether problems are design or process related.
• Conduct experiments to identify potential challenges in the process and ensure that the process meets yield, quality, and reliability standards.
• Drive continuous improvements to enhance the designs, materials, and methodologies.
• Disseminate process development information to design groups, ensuring it meets future product requirements, and extract necessary technical and device performance data for IP and SoC designs.
• Work with IP and SoC design teams to capture and optimize process requirements to enable competitive designs and products.

Requirements

• Bachelor's degree with 6+ years of experience or Master's degree with 4+ years of industry experience or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or Computer Science.
• Working knowledge of digital design and signoff.
• Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks.

Preferred Qualifications

• Strong technical understanding of semiconductor technology.
• Experience working with both Cadence and Synopsys EDA tools/flows.
• Demonstrated ability to work independently in a fast-paced environment.
• Experience in optimizing PPA for low power designs such as GPU/AI.

Qualifications

• Bachelor's degree with 6+ years of experience or Master's degree with 4+ years of industry experience or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or Computer Science.
• Minimum 3+ years of experience with the following technical skills: Working knowledge of digital design and signoff, Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks.

Benefits

Intel offers a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

$164,470.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Location

US, Oregon, Hillsboro

US, Arizona, Phoenix

US, California, Folsom

US, California, Santa Clara

US, Texas, Austin