Physical Design Engineer

About the role

NVIDIA is seeking talented Senior Physical Design Engineers to join our Networking Silicon engineering team. These engineers will develop the industry's best high-speed communication devices, focusing on the highest throughput and lowest latency.

Responsibilities

• Lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
• Work at the partition level.
• Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
• Daily work involves all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.

Requirements

• BSEE / MSEE or equivalent experience.
• 3+ years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
• Able to assist in design flow development and debugging, including application of ML/AI solutions.
• Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
• Strong analytical and debugging skills.
• Proficiency using Python, Perl, Tcl, Make scripting is helpful.
• Great teammate.

Qualifications

• Already a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.

Skills

• Experience with AI tools.

Benefits

• Competitive base salary ranging from $116,000 to $189,750 for Level 2 and $136,000 to $218,500 for Level 3.
• Equity and benefits package.

Pay

• Base salary range: $116,000 - $189,750 for Level 2, and $136,000 - $218,500 for Level 3.

Schedule

• Full-time position.