Physical Design Methodology Engineer

About the role

Advanced Design and Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tier0/tier1 customers.

Responsibilities

• Create methodologies, models, and flows for advanced design rules for a specific process node and characterize those models through silicon validation.
• Ensure IP and SoC design meets requirements and standards for a specific manufacturing process technology.
• Evaluate device performance over a range of operating conditions to identify ways to optimize silicon designs.
• Resolve prototype issues and determine whether problems are design or process related.
• Conduct experiments to identify potential challenges in the process and ensure that the process meets yield, quality, and reliability standards.
• Drive continuous improvements to enhance designs, materials, and methodologies.
• Disseminate process development information to design groups, ensuring it meets future product requirements, and extract necessary technical and device performance data for IP and SoC designs.
• Work with IP and SoC design teams to capture and optimize process requirements to enable competitive designs and products.

Requirements

• Bachelor's degree with 6+ years of experience or Master's degree with 4+ years of industry experience or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or Computer Science.
• Working knowledge of digital design and signoff.
• Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks.

Preferred Qualifications

• Strong technical understanding of semiconductor technology.
• Experience working with both Cadence and Synopsys EDA tools/flows.
• Demonstrated ability to work independently in a fast-paced environment.
• Experience in optimizing PPA for low power designs such as GPU/AI.

Qualifications

• Bachelor's degree with 6+ years of experience or Master's degree with 4+ years of industry experience or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or Computer Science.
• Working knowledge of digital design and signoff.
• Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks.

Benefits

The annual salary range for this position is $164,470.00 - 269,100.00 USD. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Pay

$164,470.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Location

US, Oregon, Hillsboro