Physical Design Engineer

About the role

Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of custom IP and SoC designs. As part of our dynamic team, you will work on cutting-edge technology to implement designs from RTL to GDS, ensuring they are ready for manufacturing.

Responsibilities

• Perform physical design implementation of custom IP and SoC designs, covering all aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
• Conduct verification and signoff processes, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyze results and recommend fixes for violations to meet product design specifications and future architecture goals.
• Optimize designs to enhance product-level parameters such as power, frequency, and area.
• Develop and improve physical design methodologies and flow automation to achieve higher efficiency and scalability.
• Collaborate with multi-disciplinary teams to address challenges in areas such as timing closure, physical clock design, multiple power domain analysis, and DFT implementation.
• Utilize industry-standard EDA tools to ensure high-quality design implementation and validation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field of study with 3+ years of hands-on experience in physical design implementation for custom IP or SoC designs OR a Master's degree in Electrical Engineering, Computer Engineering, or a related specialized field of study with 2+ years of hands-on experience in physical design implementation for custom IP or SoC design.
• Proficiency in industry-standard EDA tools for synthesis, place and route, timing analysis, and layout verification.
• Experience in physical design flows, including clock tree synthesis, floor planning, timing closure, and power integrity analysis.