Physical Design Engineer

About the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

About the Role

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering and 7+ years of ASIC Design experience, or Master’s degree in Electrical or Computer Engineering and 4+ years of ASIC Design experience, or PhD in Electrical or Computer Engineering + 1 year of ASIC Design experience.
• Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/PrimeTime, Redhawk/Voltus, or Calibre/Pegasus.

Preferred Qualifications

• Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning, and pin-assignment.
• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience with custom clock (H-Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era—and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale.

Pay

The starting salary range for this position is $167,700.00 to $245,200.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for specific locations is listed below:

• New York City Metro Area: $167,700.00 - $282,000.00
• Non-Metro New York State & Washington State: $149,100.00 - $250,900.00

For quota-based sales roles, the ranges provided include base pay and sales target incentive compensation combined.

Benefits

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include:

• Medical, dental, and vision insurance
• 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• Eligibility to receive grants of Cisco restricted stock units, which vest following continued employment for defined periods
• Paid time away, subject to Cisco’s policies:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
  • 1 paid day off for employee’s birthday
  • Paid year-end holiday shutdown
  • 4 paid days off for personal wellness
  • Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at 4.92 hours per pay period
  • Exempt employees participate in Cisco’s flexible vacation time off program with no defined limit (subject to availability and business limitations)
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward
  • Additional paid time away may be requested for critical or emergency family issues
  • Optional 10 paid days per full calendar year to volunteer
• Eligibility to earn annual bonuses, subject to Cisco’s policies (for non-sales roles)
• For sales roles, performance-based incentive pay split between quota and non-quota components, subject to the applicable Cisco plan.