Performance Engineer, Hardware

About the role

We are seeking exceptional hardware performance engineers to architect, model, and correlate high-performance custom silicon. You will develop high-fidelity simulators to predict how our AI accelerator architecture and SoC system will handle real-world AI models. You will take ownership of performance models, ISA and kernel optimization, and FPGA emulators for software development. You will be collaborating both up and down the stack with compiler, IR, and software teams, as well as with RTL design engineers.

Location: This role is based in Austin, Texas or Palo Alto, California.

Responsibilities

• Simulator Development: Design and implement high-performance and functional models of complex hardware using C++ and/or SystemC.
• Micro-architectural Exploration: Conduct "what-if" studies to evaluate architectural changes (e.g., cache sizes, branch predictors, pipeline depths, scatter/gather, matmul shaping) and their impact on IPC, MFU, TTFT, and total execution time.
• Workload Characterization: Analyze and profile AI kernels and software stacks to generate representative traces that stress-test the hardware models.
• HW/SW Co-Design: Collaborate with compiler and kernel teams to optimize software mapping to hardware, ensuring the architecture supports emerging algorithmic breakthroughs efficiently.
• Performance Correlation: Validate the performance model against RTL and pre-silicon emulators to ensure the model’s accuracy remains within strict tolerance levels.
• Bottleneck Analysis: Identify and quantify system-level bottlene