Member of Technical Staff, Hardware, Performance Engineer

About the Role

We are seeking exceptional hardware performance engineers to architect, model, and correlate high-performance custom silicon. You will develop high-fidelity simulators to predict how our AI accelerator architecture and SoC system will handle real-world AI models. You will take ownership of performance models, ISA and kernel optimization, and FPGA emulators for software development. You will collaborate both up and down the stack with compiler, IR, and software teams, as well as with RTL design engineers.

Responsibilities

• Simulator Development: Design and implement high-performance and functional models of complex hardware using C++ and/or SystemC.
• Micro-architectural Exploration: Conduct "what-if" studies to evaluate architectural changes (e.g., cache sizes, branch predictors, pipeline depths, scatter/gather, matmul shaping) and their impact on IPC, MFU, TTFT, and total execution time.
• Workload Characterization: Analyze and profile AI kernels and software stacks to generate representative traces that stress-test the hardware models.
• HW/SW Co-Design: Collaborate with compiler and kernel teams to optimize software mapping to hardware, ensuring the architecture supports emerging algorithmic breakthroughs efficiently.
• Performance Correlation: Validate the performance model against RTL and pre-silicon emulators to ensure the model’s accuracy remains within strict tolerance levels.
• Bottleneck Analysis: Identify and quantify system-level bottlenecks, ranging from instruction-level parallelism (ILP) limits to bandwidth throttling to utilization.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
• Expert proficiency in C/C++ or event-driven simulation environments like SystemC.
• Hands-on experience with how compilers transform code (LLVM/GCC/XLA) and how high-performance kernels (CUDA/Triton) interact with the underlying ISA.
• Expert knowledge in Computer Architecture of at least one style of chip, including SoCs, CPUs, GPUs, or AI accelerators.
• Experience with profiling hardware with performance counters, hardware profilers, and trace analysis tools to dissect application behavior.
• A highly collaborative mindset to push boundaries and co-design effectively with other engineers.

Preferred Qualifications

• Hands-on experience in pre-silicon RTL/emulator and/or post-silicon performance validation.
• Knowledge or experience of QEMU models for pre-silicon software development.
• Proficiency in scripting for data post-processing, visualization of simulation results, and automation of massive regression suites.

Benefits

• Generous health, dental, and vision benefits.
• Unlimited PTO.
• Relocation support as needed.

Pay

Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.

Logistics

This role is based in Austin, Texas or Palo Alto, California. We sponsor visas.